/*******************************************************************************
*              (c), Copyright 2001, Marvell International Ltd.                 *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.   *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
********************************************************************************
* prvCpssDrvExMxEventsCheetah3.h
*
* DESCRIPTION:
*       This file includes all different hardware driven Event types - Cheetah-3
*
* FILE REVISION NUMBER:
*       $Revision: 3 $
*
*******************************************************************************/
#ifndef __prvCpssDrvExMxEventsCheetah3h
#define __prvCpssDrvExMxEventsCheetah3h

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */


/***************************************************************************/

/*
 * Typedef: enum PRV_CPSS_CH3_INT_CAUSE
 *
 * Description: All interrupt cause indexes, to be used for interrupts handling,
 *              and parameters change.
 *
 * NOTE : If needed, new interrupt bits can replace the XXX_RES_i bits, in case
 *        that these bits fall into the same cause registers.
 *
 * Comment:
 *      Please see the description of each of the following interrupt event
 *      cause registers in the packet processor datasheet.
 */
typedef enum
{
    /* Global Interrupt Cause Register */
    /* Indexes 0 - 31               */
    PRV_CPSS_CH3_GLOBAL_GEN_SUM_E = 0,
    PRV_CPSS_CH3_GLOBAL_PEX_SUM_E,
    PRV_CPSS_CH3_GLOBAL_PEX_ERR_SUM_E,
    PRV_CPSS_CH3_GLOBAL_CNC_SUM_E,
    PRV_CPSS_CH3_GLOBAL_RES4_E,
    PRV_CPSS_CH3_GLOBAL_RES5_E,
    PRV_CPSS_CH3_GLOBAL_RES6_E,
    PRV_CPSS_CH3_GLOBAL_RES7_E,
    PRV_CPSS_CH3_GLOBAL_RES8_E,
    PRV_CPSS_CH3_GLOBAL_RES9_E,
    PRV_CPSS_CH3_GLOBAL_RES10_E,
    PRV_CPSS_CH3_GLOBAL_MISK_SUM_E,
    PRV_CPSS_CH3_GLOBAL_MEM_SUM_E,
    PRV_CPSS_CH3_GLOBAL_TXQ_SUM_E,
    PRV_CPSS_CH3_GLOBAL_L2I_SUM_E,
    PRV_CPSS_CH3_GLOBAL_BM_SUM0_E,
    PRV_CPSS_CH3_GLOBAL_BM_SUM1_E,
    PRV_CPSS_CH3_GLOBAL_MAC_TBL_SUM_E,
    PRV_CPSS_CH3_GLOBAL_PORTS_SUM_E,
    PRV_CPSS_CH3_GLOBAL_CPU_PORT_E,
    PRV_CPSS_CH3_GLOBAL_XG_PORTS_SUM_E,
    PRV_CPSS_CH3_GLOBAL_TX_SDMA_SUM_E,
    PRV_CPSS_CH3_GLOBAL_RX_SDMA_SUM_E,
    PRV_CPSS_CH3_GLOBAL_PCL_SUM_E,
    PRV_CPSS_CH3_GLOBAL_PLR_SUM_E,
    PRV_CPSS_CH3_GLOBAL_RES25_E,
    PRV_CPSS_CH3_GLOBAL_RES26_E,
    PRV_CPSS_CH3_GLOBAL_RES27_E,
    PRV_CPSS_CH3_GLOBAL_PRE_EGRESS_SUM_E,
    PRV_CPSS_CH3_GLOBAL_RES29_E,
    PRV_CPSS_CH3_GLOBAL_RES30_E,
    PRV_CPSS_CH3_GLOBAL_RES31_E,

    /* Miscellaneous Interrupt Cause Register */
    /* Indexes 32 - 63               */
    PRV_CPSS_CH3_MISC_SUM_E,
    PRV_CPSS_CH3_MISC_TWSI_TIME_OUT_E,
    PRV_CPSS_CH3_MISC_TWSI_STATUS_E,
    PRV_CPSS_CH3_MISC_ILLEGAL_ADDR_E,
    PRV_CPSS_CH3_MISC_CPU_PORT_RX_OVERRUN_E,
    PRV_CPSS_CH3_MISC_RES37_E,
    PRV_CPSS_CH3_MISC_RES38_E,
    PRV_CPSS_CH3_EB_AUQ_OVER_E,
    PRV_CPSS_CH3_EB_AUQ_ALMOST_FULL_E,
    PRV_CPSS_CH3_EB_AUQ_FULL_E,
    PRV_CPSS_CH3_EB_AUQ_PENDING_E,
    PRV_CPSS_CH3_EB_FUQ_FULL_E,
    PRV_CPSS_CH3_EB_FUQ_PENDING_E,
    PRV_CPSS_CH3_MISC_GENXS_READ_DMA_DONE_E,
    PRV_CPSS_CH3_MISC_RES46_E,
    PRV_CPSS_CH3_MISC_PEX_ADDR_UNMAPPED_E,
    PRV_CPSS_CH3_MISC_RES48_E,
    PRV_CPSS_CH3_MISC_RES49_E,
    PRV_CPSS_CH3_MISC_RES50_E,
    PRV_CPSS_CH3_MISC_RES51_E,
    PRV_CPSS_CH3_MISC_RES52_E,
    PRV_CPSS_CH3_MISC_RES53_E,
    PRV_CPSS_CH3_MISC_RES54_E,
    PRV_CPSS_CH3_MISC_RES55_E,
    PRV_CPSS_CH3_MISC_RES56_E,
    PRV_CPSS_CH3_MISC_RES57_E,
    PRV_CPSS_CH3_MISC_RES58_E,
    PRV_CPSS_CH3_MISC_RES59_E,
    PRV_CPSS_CH3_MISC_RES60_E,
    PRV_CPSS_CH3_MISC_RES61_E,
    PRV_CPSS_CH3_MISC_RES62_E,
    PRV_CPSS_CH3_MISC_RES63_E,

    /* GPP Interrupt Cause Register */
    /* Indexes 64 - 95               */
    PRV_CPSS_CH3_GPP_SUM_E,
    PRV_CPSS_CH3_GPP_INTERRUPT1_E,
    PRV_CPSS_CH3_GPP_INTERRUPT2_E,
    PRV_CPSS_CH3_GPP_INTERRUPT3_E,
    PRV_CPSS_CH3_GPP_INTERRUPT4_E,
    PRV_CPSS_CH3_GPP_INTERRUPT5_E,
    PRV_CPSS_CH3_GPP_INTERRUPT6_E,
    PRV_CPSS_CH3_GPP_INTERRUPT7_E,
    PRV_CPSS_CH3_GPP_INTERRUPT8_E,
    PRV_CPSS_CH3_GPP_RES73_E,
    PRV_CPSS_CH3_GPP_RES74_E,
    PRV_CPSS_CH3_GPP_RES75_E,
    PRV_CPSS_CH3_GPP_RES76_E,
    PRV_CPSS_CH3_GPP_RES77_E,
    PRV_CPSS_CH3_GPP_RES78_E,
    PRV_CPSS_CH3_GPP_RES79_E,
    PRV_CPSS_CH3_GPP_RES80_E,
    PRV_CPSS_CH3_GPP_RES81_E,
    PRV_CPSS_CH3_GPP_RES82_E,
    PRV_CPSS_CH3_GPP_RES83_E,
    PRV_CPSS_CH3_GPP_RES84_E,
    PRV_CPSS_CH3_GPP_RES85_E,
    PRV_CPSS_CH3_GPP_RES86_E,
    PRV_CPSS_CH3_GPP_RES87_E,
    PRV_CPSS_CH3_GPP_RES88_E,
    PRV_CPSS_CH3_GPP_RES89_E,
    PRV_CPSS_CH3_GPP_RES90_E,
    PRV_CPSS_CH3_GPP_RES91_E,
    PRV_CPSS_CH3_GPP_RES92_E,
    PRV_CPSS_CH3_GPP_RES93_E,
    PRV_CPSS_CH3_GPP_RES94_E,
    PRV_CPSS_CH3_GPP_RES95_E,

    /* Receive SDMA Interrupt Cause Register RxSDMAInt */
    /* Indexes 96 - 127               */

    PRV_CPSS_CH3_SDMA_RX_SUM_E,
    PRV_CPSS_CH3_SDMA_RX_RES97_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE0_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE1_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE2_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE3_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE4_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE5_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE6_E,
    PRV_CPSS_CH3_RX_BUFFER_QUEUE7_E,
    PRV_CPSS_CH3_SDMA_RX_RES106_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE0_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE1_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE2_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE3_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE4_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE5_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE6_E,
    PRV_CPSS_CH3_RX_ERR_QUEUE7_E,
    PRV_CPSS_CH3_SDMA_RX_ERROR_RES_CNT_OFF_E,
    PRV_CPSS_CH3_SDMA_RX_BYTE_CNT_OFF_E,
    PRV_CPSS_CH3_SDMA_RX_PACKET_CNT_OFF_E,
    PRV_CPSS_CH3_SDMA_RX_RES118_E,
    PRV_CPSS_CH3_SDMA_RX_RES119_E,
    PRV_CPSS_CH3_SDMA_RX_RES120_E,
    PRV_CPSS_CH3_SDMA_RX_RES121_E,
    PRV_CPSS_CH3_SDMA_RX_RES122_E,
    PRV_CPSS_CH3_SDMA_RX_RES123_E,
    PRV_CPSS_CH3_SDMA_RX_RES124_E,
    PRV_CPSS_CH3_SDMA_RX_RES125_E,
    PRV_CPSS_CH3_SDMA_RX_RES126_E,
    PRV_CPSS_CH3_SDMA_RX_RES127_E,


    /* Transmit SDMA Interrupt Cause Register TxSDMAInt */
    /* Indexes 128 - 159               */

    PRV_CPSS_CH3_SDMA_TX_SUM_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE0_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE1_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE2_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE3_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE4_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE5_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE6_E,
    PRV_CPSS_CH3_TX_BUFFER_QUEUE7_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE0_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE1_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE2_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE3_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE4_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE5_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE6_E,
    PRV_CPSS_CH3_TX_ERR_QUEUE7_E,
    PRV_CPSS_CH3_TX_END_QUEUE0_E,
    PRV_CPSS_CH3_TX_END_QUEUE1_E,
    PRV_CPSS_CH3_TX_END_QUEUE2_E,
    PRV_CPSS_CH3_TX_END_QUEUE3_E,
    PRV_CPSS_CH3_TX_END_QUEUE4_E,
    PRV_CPSS_CH3_TX_END_QUEUE5_E,
    PRV_CPSS_CH3_TX_END_QUEUE6_E,
    PRV_CPSS_CH3_TX_END_QUEUE7_E,
    PRV_CPSS_CH3_SDMA_TX_RES153_E,
    PRV_CPSS_CH3_SDMA_TX_RES154_E,
    PRV_CPSS_CH3_SDMA_TX_RES155_E,
    PRV_CPSS_CH3_SDMA_TX_RES156_E,
    PRV_CPSS_CH3_SDMA_TX_RES157_E,
    PRV_CPSS_CH3_SDMA_TX_RES158_E,
    PRV_CPSS_CH3_SDMA_TX_RES159_E,


    /* (PEX) PCI Express Interrupt Cause Register */
    /* Indexes 160 - 191               */

    PRV_CPSS_CH3_PEX_DL_DOWN_TX_ACC_ERR_E,
    PRV_CPSS_CH3_PEX_MASTER_DISABLED_E,
    PRV_CPSS_CH3_PEX_RES162_E,
    PRV_CPSS_CH3_PEX_ERROR_WR_TO_REG_E,
    PRV_CPSS_CH3_PEX_HIT_DEFAULT_WIN_ERR_E,
    PRV_CPSS_CH3_PEX_RES165_E,
    PRV_CPSS_CH3_PEX_RES166_E,
    PRV_CPSS_CH3_PEX_RES167_E,
    PRV_CPSS_CH3_PEX_COR_ERROR_DET_E,
    PRV_CPSS_CH3_PEX_NON_FATAL_ERROR_DET_E,
    PRV_CPSS_CH3_PEX_FATAL_ERROR_DET_E,
    PRV_CPSS_CH3_PEX_DSTATE_CHANGED_E,
    PRV_CPSS_CH3_PEX_BIST_E,
    PRV_CPSS_CH3_PEX_RES173_E,
    PRV_CPSS_CH3_PEX_RES174_E,
    PRV_CPSS_CH3_PEX_RES175_E,
    PRV_CPSS_CH3_PEX_RCV_ERROR_FATAL_E,
    PRV_CPSS_CH3_PEX_RCV_ERROR_NON_FATAL_E,
    PRV_CPSS_CH3_PEX_RCV_ERROR_COR_E,
    PRV_CPSS_CH3_PEX_RCV_CRS_E,
    PRV_CPSS_CH3_PEX_PEX_SLAVE_HOT_RESET_E,
    PRV_CPSS_CH3_PEX_PEX_SLAVE_DISABLE_LINK_E,
    PRV_CPSS_CH3_PEX_PEX_SLAVE_LOOPBACK_E,
    PRV_CPSS_CH3_PEX_PEX_LINK_FAIL_E,
    PRV_CPSS_CH3_PEX_RCV_A_E,
    PRV_CPSS_CH3_PEX_RCV_B_E,
    PRV_CPSS_CH3_PEX_RCV_C_E,
    PRV_CPSS_CH3_PEX_RCV_D_E,
    PRV_CPSS_CH3_PEX_RES188_E,
    PRV_CPSS_CH3_PEX_RES189_E,
    PRV_CPSS_CH3_PEX_RES190_E,
    PRV_CPSS_CH3_PEX_RES191_E,

    /* Tri-speed Ports and MIB Counters Summary Register */
    /* Indexes 192 - 223               */

    PRV_CPSS_CH3_3SPPMIB_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_GOP0MIB_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_GOP1MIB_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_GOP2MIB_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_GOP3MIB_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_PORTS_SUM_E,
    PRV_CPSS_CH3_3SPPMIB_RES198_E,
    PRV_CPSS_CH3_3SPPMIB_RES199_E,
    PRV_CPSS_CH3_3SPPMIB_RES200_E,
    PRV_CPSS_CH3_3SPPMIB_RES201_E,
    PRV_CPSS_CH3_3SPPMIB_RES202_E,
    PRV_CPSS_CH3_3SPPMIB_RES203_E,
    PRV_CPSS_CH3_3SPPMIB_RES204_E,
    PRV_CPSS_CH3_3SPPMIB_RES205_E,
    PRV_CPSS_CH3_3SPPMIB_RES206_E,
    PRV_CPSS_CH3_3SPPMIB_RES207_E,
    PRV_CPSS_CH3_3SPPMIB_RES208_E,
    PRV_CPSS_CH3_3SPPMIB_RES209_E,
    PRV_CPSS_CH3_3SPPMIB_RES210_E,
    PRV_CPSS_CH3_3SPPMIB_RES211_E,
    PRV_CPSS_CH3_3SPPMIB_RES212_E,
    PRV_CPSS_CH3_3SPPMIB_RES213_E,
    PRV_CPSS_CH3_3SPPMIB_RES214_E,
    PRV_CPSS_CH3_3SPPMIB_RES215_E,
    PRV_CPSS_CH3_3SPPMIB_RES216_E,
    PRV_CPSS_CH3_3SPPMIB_RES217_E,
    PRV_CPSS_CH3_3SPPMIB_RES218_E,
    PRV_CPSS_CH3_3SPPMIB_RES219_E,
    PRV_CPSS_CH3_3SPPMIB_RES220_E,
    PRV_CPSS_CH3_3SPPMIB_RES221_E,
    PRV_CPSS_CH3_3SPPMIB_RES222_E,
    PRV_CPSS_CH3_3SPPMIB_RES223_E,

    /* Tree Speed Ports Interrupt Summary Register */
    /* Indexes 224 - 255 */

    PRV_CPSS_CH3_3SPP_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT0_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT1_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT2_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT3_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT4_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT5_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT6_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT7_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT8_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT9_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT10_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT11_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT12_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT13_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT14_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT15_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT16_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT17_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT18_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT19_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT20_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT21_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT22_SUM_E,
    PRV_CPSS_CH3_3SPP_PORT23_SUM_E,
    PRV_CPSS_CH3_3SPP_RES249_E,
    PRV_CPSS_CH3_3SPP_RES250_E,
    PRV_CPSS_CH3_3SPP_RES251_E,
    PRV_CPSS_CH3_3SPP_RES252_E,
    PRV_CPSS_CH3_3SPP_RES253_E,
    PRV_CPSS_CH3_3SPP_RES254_E,
    PRV_CPSS_CH3_3SPP_RES255_E,

    /* Port 0 Interrupt Cause Register */
    /* Indexes 256 - 287               */

    PRV_CPSS_CH3_PORT_0_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT0_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT0_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT0_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT0_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT0_E,
    PRV_CPSS_CH3_PORT_0_RES266_E,
    PRV_CPSS_CH3_PORT_0_RES267_E,
    PRV_CPSS_CH3_PORT_0_RES268_E,
    PRV_CPSS_CH3_PORT_0_RES269_E,
    PRV_CPSS_CH3_PORT_0_RES270_E,
    PRV_CPSS_CH3_PORT_0_RES271_E,
    PRV_CPSS_CH3_PORT_0_RES272_E,
    PRV_CPSS_CH3_PORT_0_RES273_E,
    PRV_CPSS_CH3_PORT_0_RES274_E,
    PRV_CPSS_CH3_PORT_0_RES275_E,
    PRV_CPSS_CH3_PORT_0_RES276_E,
    PRV_CPSS_CH3_PORT_0_RES277_E,
    PRV_CPSS_CH3_PORT_0_RES278_E,
    PRV_CPSS_CH3_PORT_0_RES279_E,
    PRV_CPSS_CH3_PORT_0_RES280_E,
    PRV_CPSS_CH3_PORT_0_RES281_E,
    PRV_CPSS_CH3_PORT_0_RES282_E,
    PRV_CPSS_CH3_PORT_0_RES283_E,
    PRV_CPSS_CH3_PORT_0_RES284_E,
    PRV_CPSS_CH3_PORT_0_RES285_E,
    PRV_CPSS_CH3_PORT_0_RES286_E,
    PRV_CPSS_CH3_PORT_0_RES287_E,

    /* Port 1 Interrupt Cause Register */
    /* Indexes 288 - 319               */

    PRV_CPSS_CH3_PORT_1_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT1_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT1_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT1_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT1_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT1_E,
    PRV_CPSS_CH3_PORT_1_RES298_E,
    PRV_CPSS_CH3_PORT_1_RES299_E,
    PRV_CPSS_CH3_PORT_1_RES300_E,
    PRV_CPSS_CH3_PORT_1_RES301_E,
    PRV_CPSS_CH3_PORT_1_RES302_E,
    PRV_CPSS_CH3_PORT_1_RES303_E,
    PRV_CPSS_CH3_PORT_1_RES304_E,
    PRV_CPSS_CH3_PORT_1_RES305_E,
    PRV_CPSS_CH3_PORT_1_RES306_E,
    PRV_CPSS_CH3_PORT_1_RES307_E,
    PRV_CPSS_CH3_PORT_1_RES308_E,
    PRV_CPSS_CH3_PORT_1_RES309_E,
    PRV_CPSS_CH3_PORT_1_RES310_E,
    PRV_CPSS_CH3_PORT_1_RES311_E,
    PRV_CPSS_CH3_PORT_1_RES312_E,
    PRV_CPSS_CH3_PORT_1_RES313_E,
    PRV_CPSS_CH3_PORT_1_RES314_E,
    PRV_CPSS_CH3_PORT_1_RES315_E,
    PRV_CPSS_CH3_PORT_1_RES316_E,
    PRV_CPSS_CH3_PORT_1_RES317_E,
    PRV_CPSS_CH3_PORT_1_RES318_E,
    PRV_CPSS_CH3_PORT_1_RES319_E,

    /* Port 2 Interrupt Cause Register */
    /* Indexes 320 - 351               */

    PRV_CPSS_CH3_PORT_2_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT2_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT2_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT2_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT2_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT2_E,
    PRV_CPSS_CH3_PORT_2_RES330_E,
    PRV_CPSS_CH3_PORT_2_RES331_E,
    PRV_CPSS_CH3_PORT_2_RES332_E,
    PRV_CPSS_CH3_PORT_2_RES333_E,
    PRV_CPSS_CH3_PORT_2_RES334_E,
    PRV_CPSS_CH3_PORT_2_RES335_E,
    PRV_CPSS_CH3_PORT_2_RES336_E,
    PRV_CPSS_CH3_PORT_2_RES337_E,
    PRV_CPSS_CH3_PORT_2_RES338_E,
    PRV_CPSS_CH3_PORT_2_RES339_E,
    PRV_CPSS_CH3_PORT_2_RES340_E,
    PRV_CPSS_CH3_PORT_2_RES341_E,
    PRV_CPSS_CH3_PORT_2_RES342_E,
    PRV_CPSS_CH3_PORT_2_RES343_E,
    PRV_CPSS_CH3_PORT_2_RES344_E,
    PRV_CPSS_CH3_PORT_2_RES345_E,
    PRV_CPSS_CH3_PORT_2_RES346_E,
    PRV_CPSS_CH3_PORT_2_RES347_E,
    PRV_CPSS_CH3_PORT_2_RES348_E,
    PRV_CPSS_CH3_PORT_2_RES349_E,
    PRV_CPSS_CH3_PORT_2_RES350_E,
    PRV_CPSS_CH3_PORT_2_RES351_E,

    /* Port 3 Interrupt Cause Register */
    /* Indexes 352 - 383               */

    PRV_CPSS_CH3_PORT_3_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT3_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT3_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT3_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT3_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT3_E,
    PRV_CPSS_CH3_PORT_3_RES362_E,
    PRV_CPSS_CH3_PORT_3_RES363_E,
    PRV_CPSS_CH3_PORT_3_RES364_E,
    PRV_CPSS_CH3_PORT_3_RES365_E,
    PRV_CPSS_CH3_PORT_3_RES366_E,
    PRV_CPSS_CH3_PORT_3_RES367_E,
    PRV_CPSS_CH3_PORT_3_RES368_E,
    PRV_CPSS_CH3_PORT_3_RES369_E,
    PRV_CPSS_CH3_PORT_3_RES370_E,
    PRV_CPSS_CH3_PORT_3_RES371_E,
    PRV_CPSS_CH3_PORT_3_RES372_E,
    PRV_CPSS_CH3_PORT_3_RES373_E,
    PRV_CPSS_CH3_PORT_3_RES374_E,
    PRV_CPSS_CH3_PORT_3_RES375_E,
    PRV_CPSS_CH3_PORT_3_RES376_E,
    PRV_CPSS_CH3_PORT_3_RES377_E,
    PRV_CPSS_CH3_PORT_3_RES378_E,
    PRV_CPSS_CH3_PORT_3_RES379_E,
    PRV_CPSS_CH3_PORT_3_RES380_E,
    PRV_CPSS_CH3_PORT_3_RES381_E,
    PRV_CPSS_CH3_PORT_3_RES382_E,
    PRV_CPSS_CH3_PORT_3_RES383_E,

    /* Port 4 Interrupt Cause Register */
    /* Indexes 384 - 415               */

    PRV_CPSS_CH3_PORT_4_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT4_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT4_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT4_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT4_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT4_E,
    PRV_CPSS_CH3_PORT_4_RES394_E,
    PRV_CPSS_CH3_PORT_4_RES395_E,
    PRV_CPSS_CH3_PORT_4_RES396_E,
    PRV_CPSS_CH3_PORT_4_RES397_E,
    PRV_CPSS_CH3_PORT_4_RES398_E,
    PRV_CPSS_CH3_PORT_4_RES399_E,
    PRV_CPSS_CH3_PORT_4_RES400_E,
    PRV_CPSS_CH3_PORT_4_RES401_E,
    PRV_CPSS_CH3_PORT_4_RES402_E,
    PRV_CPSS_CH3_PORT_4_RES403_E,
    PRV_CPSS_CH3_PORT_4_RES404_E,
    PRV_CPSS_CH3_PORT_4_RES405_E,
    PRV_CPSS_CH3_PORT_4_RES406_E,
    PRV_CPSS_CH3_PORT_4_RES407_E,
    PRV_CPSS_CH3_PORT_4_RES408_E,
    PRV_CPSS_CH3_PORT_4_RES409_E,
    PRV_CPSS_CH3_PORT_4_RES410_E,
    PRV_CPSS_CH3_PORT_4_RES411_E,
    PRV_CPSS_CH3_PORT_4_RES412_E,
    PRV_CPSS_CH3_PORT_4_RES413_E,
    PRV_CPSS_CH3_PORT_4_RES414_E,
    PRV_CPSS_CH3_PORT_4_RES415_E,

    /* Port 5 Interrupt Cause Register */
    /* Indexes 416 - 447               */

    PRV_CPSS_CH3_PORT_5_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT5_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT5_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT5_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT5_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT5_E,
    PRV_CPSS_CH3_PORT_5_RES426_E,
    PRV_CPSS_CH3_PORT_5_RES427_E,
    PRV_CPSS_CH3_PORT_5_RES428_E,
    PRV_CPSS_CH3_PORT_5_RES429_E,
    PRV_CPSS_CH3_PORT_5_RES430_E,
    PRV_CPSS_CH3_PORT_5_RES431_E,
    PRV_CPSS_CH3_PORT_5_RES432_E,
    PRV_CPSS_CH3_PORT_5_RES433_E,
    PRV_CPSS_CH3_PORT_5_RES434_E,
    PRV_CPSS_CH3_PORT_5_RES435_E,
    PRV_CPSS_CH3_PORT_5_RES436_E,
    PRV_CPSS_CH3_PORT_5_RES437_E,
    PRV_CPSS_CH3_PORT_5_RES438_E,
    PRV_CPSS_CH3_PORT_5_RES439_E,
    PRV_CPSS_CH3_PORT_5_RES440_E,
    PRV_CPSS_CH3_PORT_5_RES441_E,
    PRV_CPSS_CH3_PORT_5_RES442_E,
    PRV_CPSS_CH3_PORT_5_RES443_E,
    PRV_CPSS_CH3_PORT_5_RES444_E,
    PRV_CPSS_CH3_PORT_5_RES445_E,
    PRV_CPSS_CH3_PORT_5_RES446_E,
    PRV_CPSS_CH3_PORT_5_RES447_E,

    /* Port 6 Interrupt Cause Register */
    /* Indexes 448 - 479               */

    PRV_CPSS_CH3_PORT_6_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT6_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT6_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT6_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT6_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT6_E,
    PRV_CPSS_CH3_PORT_6_RES458_E,
    PRV_CPSS_CH3_PORT_6_RES459_E,
    PRV_CPSS_CH3_PORT_6_RES460_E,
    PRV_CPSS_CH3_PORT_6_RES461_E,
    PRV_CPSS_CH3_PORT_6_RES462_E,
    PRV_CPSS_CH3_PORT_6_RES463_E,
    PRV_CPSS_CH3_PORT_6_RES464_E,
    PRV_CPSS_CH3_PORT_6_RES465_E,
    PRV_CPSS_CH3_PORT_6_RES466_E,
    PRV_CPSS_CH3_PORT_6_RES467_E,
    PRV_CPSS_CH3_PORT_6_RES468_E,
    PRV_CPSS_CH3_PORT_6_RES469_E,
    PRV_CPSS_CH3_PORT_6_RES470_E,
    PRV_CPSS_CH3_PORT_6_RES471_E,
    PRV_CPSS_CH3_PORT_6_RES472_E,
    PRV_CPSS_CH3_PORT_6_RES473_E,
    PRV_CPSS_CH3_PORT_6_RES474_E,
    PRV_CPSS_CH3_PORT_6_RES475_E,
    PRV_CPSS_CH3_PORT_6_RES476_E,
    PRV_CPSS_CH3_PORT_6_RES477_E,
    PRV_CPSS_CH3_PORT_6_RES478_E,
    PRV_CPSS_CH3_PORT_6_RES479_E,

    /* Port 7 Interrupt Cause Register */
    /* Indexes 480 - 511               */

    PRV_CPSS_CH3_PORT_7_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT7_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT7_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT7_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT7_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT7_E,
    PRV_CPSS_CH3_PORT_7_RES490_E,
    PRV_CPSS_CH3_PORT_7_RES491_E,
    PRV_CPSS_CH3_PORT_7_RES492_E,
    PRV_CPSS_CH3_PORT_7_RES493_E,
    PRV_CPSS_CH3_PORT_7_RES494_E,
    PRV_CPSS_CH3_PORT_7_RES495_E,
    PRV_CPSS_CH3_PORT_7_RES496_E,
    PRV_CPSS_CH3_PORT_7_RES497_E,
    PRV_CPSS_CH3_PORT_7_RES498_E,
    PRV_CPSS_CH3_PORT_7_RES499_E,
    PRV_CPSS_CH3_PORT_7_RES500_E,
    PRV_CPSS_CH3_PORT_7_RES501_E,
    PRV_CPSS_CH3_PORT_7_RES502_E,
    PRV_CPSS_CH3_PORT_7_RES503_E,
    PRV_CPSS_CH3_PORT_7_RES504_E,
    PRV_CPSS_CH3_PORT_7_RES505_E,
    PRV_CPSS_CH3_PORT_7_RES506_E,
    PRV_CPSS_CH3_PORT_7_RES507_E,
    PRV_CPSS_CH3_PORT_7_RES508_E,
    PRV_CPSS_CH3_PORT_7_RES509_E,
    PRV_CPSS_CH3_PORT_7_RES510_E,
    PRV_CPSS_CH3_PORT_7_RES511_E,

    /* Port 8 Interrupt Cause Register */
    /* Indexes 512 - 543               */

    PRV_CPSS_CH3_PORT_8_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT8_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT8_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT8_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT8_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT8_E,
    PRV_CPSS_CH3_PORT_8_RES522_E,
    PRV_CPSS_CH3_PORT_8_RES523_E,
    PRV_CPSS_CH3_PORT_8_RES524_E,
    PRV_CPSS_CH3_PORT_8_RES525_E,
    PRV_CPSS_CH3_PORT_8_RES526_E,
    PRV_CPSS_CH3_PORT_8_RES527_E,
    PRV_CPSS_CH3_PORT_8_RES528_E,
    PRV_CPSS_CH3_PORT_8_RES529_E,
    PRV_CPSS_CH3_PORT_8_RES530_E,
    PRV_CPSS_CH3_PORT_8_RES531_E,
    PRV_CPSS_CH3_PORT_8_RES532_E,
    PRV_CPSS_CH3_PORT_8_RES533_E,
    PRV_CPSS_CH3_PORT_8_RES534_E,
    PRV_CPSS_CH3_PORT_8_RES535_E,
    PRV_CPSS_CH3_PORT_8_RES536_E,
    PRV_CPSS_CH3_PORT_8_RES537_E,
    PRV_CPSS_CH3_PORT_8_RES538_E,
    PRV_CPSS_CH3_PORT_8_RES539_E,
    PRV_CPSS_CH3_PORT_8_RES540_E,
    PRV_CPSS_CH3_PORT_8_RES541_E,
    PRV_CPSS_CH3_PORT_8_RES542_E,
    PRV_CPSS_CH3_PORT_8_RES543_E,

    /* Port 9 Interrupt Cause Register */
    /* Indexes 544 - 575                */

    PRV_CPSS_CH3_PORT_9_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT9_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT9_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT9_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT9_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT9_E,
    PRV_CPSS_CH3_PORT_9_RES554_E,
    PRV_CPSS_CH3_PORT_9_RES555_E,
    PRV_CPSS_CH3_PORT_9_RES556_E,
    PRV_CPSS_CH3_PORT_9_RES557_E,
    PRV_CPSS_CH3_PORT_9_RES558_E,
    PRV_CPSS_CH3_PORT_9_RES559_E,
    PRV_CPSS_CH3_PORT_9_RES560_E,
    PRV_CPSS_CH3_PORT_9_RES561_E,
    PRV_CPSS_CH3_PORT_9_RES562_E,
    PRV_CPSS_CH3_PORT_9_RES563_E,
    PRV_CPSS_CH3_PORT_9_RES564_E,
    PRV_CPSS_CH3_PORT_9_RES565_E,
    PRV_CPSS_CH3_PORT_9_RES566_E,
    PRV_CPSS_CH3_PORT_9_RES567_E,
    PRV_CPSS_CH3_PORT_9_RES568_E,
    PRV_CPSS_CH3_PORT_9_RES569_E,
    PRV_CPSS_CH3_PORT_9_RES570_E,
    PRV_CPSS_CH3_PORT_9_RES571_E,
    PRV_CPSS_CH3_PORT_9_RES572_E,
    PRV_CPSS_CH3_PORT_9_RES573_E,
    PRV_CPSS_CH3_PORT_9_RES574_E,
    PRV_CPSS_CH3_PORT_9_RES575_E,

    /* Port 10 Interrupt Cause Register */
    /* Indexes 576 - 607                */

    PRV_CPSS_CH3_PORT_10_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT10_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT10_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT10_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT10_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT10_E,
    PRV_CPSS_CH3_PORT_10_RES586_E,
    PRV_CPSS_CH3_PORT_10_RES587_E,
    PRV_CPSS_CH3_PORT_10_RES588_E,
    PRV_CPSS_CH3_PORT_10_RES589_E,
    PRV_CPSS_CH3_PORT_10_RES590_E,
    PRV_CPSS_CH3_PORT_10_RES591_E,
    PRV_CPSS_CH3_PORT_10_RES592_E,
    PRV_CPSS_CH3_PORT_10_RES593_E,
    PRV_CPSS_CH3_PORT_10_RES594_E,
    PRV_CPSS_CH3_PORT_10_RES595_E,
    PRV_CPSS_CH3_PORT_10_RES596_E,
    PRV_CPSS_CH3_PORT_10_RES597_E,
    PRV_CPSS_CH3_PORT_10_RES598_E,
    PRV_CPSS_CH3_PORT_10_RES599_E,
    PRV_CPSS_CH3_PORT_10_RES600_E,
    PRV_CPSS_CH3_PORT_10_RES601_E,
    PRV_CPSS_CH3_PORT_10_RES602_E,
    PRV_CPSS_CH3_PORT_10_RES603_E,
    PRV_CPSS_CH3_PORT_10_RES604_E,
    PRV_CPSS_CH3_PORT_10_RES605_E,
    PRV_CPSS_CH3_PORT_10_RES606_E,
    PRV_CPSS_CH3_PORT_10_RES607_E,

    /* Port 11 Interrupt Cause Register */
    /* Indexes 608 - 639                */

    PRV_CPSS_CH3_PORT_11_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT11_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT11_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT11_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT11_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT11_E,
    PRV_CPSS_CH3_PORT_11_RES618_E,
    PRV_CPSS_CH3_PORT_11_RES619_E,
    PRV_CPSS_CH3_PORT_11_RES620_E,
    PRV_CPSS_CH3_PORT_11_RES621_E,
    PRV_CPSS_CH3_PORT_11_RES622_E,
    PRV_CPSS_CH3_PORT_11_RES623_E,
    PRV_CPSS_CH3_PORT_11_RES624_E,
    PRV_CPSS_CH3_PORT_11_RES625_E,
    PRV_CPSS_CH3_PORT_11_RES626_E,
    PRV_CPSS_CH3_PORT_11_RES627_E,
    PRV_CPSS_CH3_PORT_11_RES628_E,
    PRV_CPSS_CH3_PORT_11_RES629_E,
    PRV_CPSS_CH3_PORT_11_RES630_E,
    PRV_CPSS_CH3_PORT_11_RES631_E,
    PRV_CPSS_CH3_PORT_11_RES632_E,
    PRV_CPSS_CH3_PORT_11_RES633_E,
    PRV_CPSS_CH3_PORT_11_RES634_E,
    PRV_CPSS_CH3_PORT_11_RES635_E,
    PRV_CPSS_CH3_PORT_11_RES636_E,
    PRV_CPSS_CH3_PORT_11_RES637_E,
    PRV_CPSS_CH3_PORT_11_RES638_E,
    PRV_CPSS_CH3_PORT_11_RES639_E,

    /* Port 12 Interrupt Cause Register */
    /* Indexes 640 - 671                */

    PRV_CPSS_CH3_PORT_12_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT12_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT12_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT12_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT12_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT12_E,
    PRV_CPSS_CH3_PORT_12_RES650_E,
    PRV_CPSS_CH3_PORT_12_RES651_E,
    PRV_CPSS_CH3_PORT_12_RES652_E,
    PRV_CPSS_CH3_PORT_12_RES653_E,
    PRV_CPSS_CH3_PORT_12_RES654_E,
    PRV_CPSS_CH3_PORT_12_RES655_E,
    PRV_CPSS_CH3_PORT_12_RES656_E,
    PRV_CPSS_CH3_PORT_12_RES657_E,
    PRV_CPSS_CH3_PORT_12_RES658_E,
    PRV_CPSS_CH3_PORT_12_RES659_E,
    PRV_CPSS_CH3_PORT_12_RES660_E,
    PRV_CPSS_CH3_PORT_12_RES661_E,
    PRV_CPSS_CH3_PORT_12_RES662_E,
    PRV_CPSS_CH3_PORT_12_RES663_E,
    PRV_CPSS_CH3_PORT_12_RES664_E,
    PRV_CPSS_CH3_PORT_12_RES665_E,
    PRV_CPSS_CH3_PORT_12_RES666_E,
    PRV_CPSS_CH3_PORT_12_RES667_E,
    PRV_CPSS_CH3_PORT_12_RES668_E,
    PRV_CPSS_CH3_PORT_12_RES669_E,
    PRV_CPSS_CH3_PORT_12_RES670_E,
    PRV_CPSS_CH3_PORT_12_RES671_E,

    /* Port 13 Interrupt Cause Register */
    /* Indexes 672 - 703                */

    PRV_CPSS_CH3_PORT_13_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT13_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT13_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT13_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT13_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT13_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT13_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT13_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT13_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT13_E,
    PRV_CPSS_CH3_PORT_13_RES682_E,
    PRV_CPSS_CH3_PORT_13_RES683_E,
    PRV_CPSS_CH3_PORT_13_RES684_E,
    PRV_CPSS_CH3_PORT_13_RES685_E,
    PRV_CPSS_CH3_PORT_13_RES686_E,
    PRV_CPSS_CH3_PORT_13_RES687_E,
    PRV_CPSS_CH3_PORT_13_RES688_E,
    PRV_CPSS_CH3_PORT_13_RES689_E,
    PRV_CPSS_CH3_PORT_13_RES690_E,
    PRV_CPSS_CH3_PORT_13_RES691_E,
    PRV_CPSS_CH3_PORT_13_RES692_E,
    PRV_CPSS_CH3_PORT_13_RES693_E,
    PRV_CPSS_CH3_PORT_13_RES694_E,
    PRV_CPSS_CH3_PORT_13_RES695_E,
    PRV_CPSS_CH3_PORT_13_RES696_E,
    PRV_CPSS_CH3_PORT_13_RES697_E,
    PRV_CPSS_CH3_PORT_13_RES698_E,
    PRV_CPSS_CH3_PORT_13_RES699_E,
    PRV_CPSS_CH3_PORT_13_RES700_E,
    PRV_CPSS_CH3_PORT_13_RES701_E,
    PRV_CPSS_CH3_PORT_13_RES702_E,
    PRV_CPSS_CH3_PORT_13_RES703_E,

    /* Port 14 Interrupt Cause Register */
    /* Indexes 704 - 735                */

    PRV_CPSS_CH3_PORT_14_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT14_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT14_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT14_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT14_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT14_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT14_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT14_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT14_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT14_E,
    PRV_CPSS_CH3_PORT_14_RES714_E,
    PRV_CPSS_CH3_PORT_14_RES715_E,
    PRV_CPSS_CH3_PORT_14_RES716_E,
    PRV_CPSS_CH3_PORT_14_RES717_E,
    PRV_CPSS_CH3_PORT_14_RES718_E,
    PRV_CPSS_CH3_PORT_14_RES719_E,
    PRV_CPSS_CH3_PORT_14_RES720_E,
    PRV_CPSS_CH3_PORT_14_RES721_E,
    PRV_CPSS_CH3_PORT_14_RES722_E,
    PRV_CPSS_CH3_PORT_14_RES723_E,
    PRV_CPSS_CH3_PORT_14_RES724_E,
    PRV_CPSS_CH3_PORT_14_RES725_E,
    PRV_CPSS_CH3_PORT_14_RES726_E,
    PRV_CPSS_CH3_PORT_14_RES727_E,
    PRV_CPSS_CH3_PORT_14_RES728_E,
    PRV_CPSS_CH3_PORT_14_RES729_E,
    PRV_CPSS_CH3_PORT_14_RES730_E,
    PRV_CPSS_CH3_PORT_14_RES731_E,
    PRV_CPSS_CH3_PORT_14_RES732_E,
    PRV_CPSS_CH3_PORT_14_RES733_E,
    PRV_CPSS_CH3_PORT_14_RES734_E,
    PRV_CPSS_CH3_PORT_14_RES735_E,

    /* Port 15 Interrupt Cause Register */
    /* Indexes 736 - 767                */

    PRV_CPSS_CH3_PORT_15_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT15_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT15_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT15_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT15_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT15_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT15_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT15_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT15_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT15_E,
    PRV_CPSS_CH3_PORT_15_RES746_E,
    PRV_CPSS_CH3_PORT_15_RES747_E,
    PRV_CPSS_CH3_PORT_15_RES748_E,
    PRV_CPSS_CH3_PORT_15_RES749_E,
    PRV_CPSS_CH3_PORT_15_RES750_E,
    PRV_CPSS_CH3_PORT_15_RES751_E,
    PRV_CPSS_CH3_PORT_15_RES752_E,
    PRV_CPSS_CH3_PORT_15_RES753_E,
    PRV_CPSS_CH3_PORT_15_RES754_E,
    PRV_CPSS_CH3_PORT_15_RES755_E,
    PRV_CPSS_CH3_PORT_15_RES756_E,
    PRV_CPSS_CH3_PORT_15_RES757_E,
    PRV_CPSS_CH3_PORT_15_RES758_E,
    PRV_CPSS_CH3_PORT_15_RES759_E,
    PRV_CPSS_CH3_PORT_15_RES760_E,
    PRV_CPSS_CH3_PORT_15_RES761_E,
    PRV_CPSS_CH3_PORT_15_RES762_E,
    PRV_CPSS_CH3_PORT_15_RES763_E,
    PRV_CPSS_CH3_PORT_15_RES764_E,
    PRV_CPSS_CH3_PORT_15_RES765_E,
    PRV_CPSS_CH3_PORT_15_RES766_E,
    PRV_CPSS_CH3_PORT_15_RES767_E,

    /* Port 16 Interrupt Cause Register */
    /* Indexes 768 - 799                */

    PRV_CPSS_CH3_PORT_16_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT16_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT16_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT16_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT16_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT16_E,
    PRV_CPSS_CH3_PORT_16_RES778_E,
    PRV_CPSS_CH3_PORT_16_RES779_E,
    PRV_CPSS_CH3_PORT_16_RES780_E,
    PRV_CPSS_CH3_PORT_16_RES781_E,
    PRV_CPSS_CH3_PORT_16_RES782_E,
    PRV_CPSS_CH3_PORT_16_RES783_E,
    PRV_CPSS_CH3_PORT_16_RES784_E,
    PRV_CPSS_CH3_PORT_16_RES785_E,
    PRV_CPSS_CH3_PORT_16_RES786_E,
    PRV_CPSS_CH3_PORT_16_RES787_E,
    PRV_CPSS_CH3_PORT_16_RES788_E,
    PRV_CPSS_CH3_PORT_16_RES789_E,
    PRV_CPSS_CH3_PORT_16_RES790_E,
    PRV_CPSS_CH3_PORT_16_RES791_E,
    PRV_CPSS_CH3_PORT_16_RES792_E,
    PRV_CPSS_CH3_PORT_16_RES793_E,
    PRV_CPSS_CH3_PORT_16_RES794_E,
    PRV_CPSS_CH3_PORT_16_RES795_E,
    PRV_CPSS_CH3_PORT_16_RES796_E,
    PRV_CPSS_CH3_PORT_16_RES797_E,
    PRV_CPSS_CH3_PORT_16_RES798_E,
    PRV_CPSS_CH3_PORT_16_RES799_E,

    /* Port 17 Interrupt Cause Register */
    /* Indexes 800 - 831                */

    PRV_CPSS_CH3_PORT_17_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT17_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT17_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT17_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT17_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT17_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT17_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT17_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT17_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT17_E,
    PRV_CPSS_CH3_PORT_17_RES810_E,
    PRV_CPSS_CH3_PORT_17_RES811_E,
    PRV_CPSS_CH3_PORT_17_RES812_E,
    PRV_CPSS_CH3_PORT_17_RES813_E,
    PRV_CPSS_CH3_PORT_17_RES814_E,
    PRV_CPSS_CH3_PORT_17_RES815_E,
    PRV_CPSS_CH3_PORT_17_RES816_E,
    PRV_CPSS_CH3_PORT_17_RES817_E,
    PRV_CPSS_CH3_PORT_17_RES818_E,
    PRV_CPSS_CH3_PORT_17_RES819_E,
    PRV_CPSS_CH3_PORT_17_RES820_E,
    PRV_CPSS_CH3_PORT_17_RES821_E,
    PRV_CPSS_CH3_PORT_17_RES822_E,
    PRV_CPSS_CH3_PORT_17_RES823_E,
    PRV_CPSS_CH3_PORT_17_RES824_E,
    PRV_CPSS_CH3_PORT_17_RES825_E,
    PRV_CPSS_CH3_PORT_17_RES826_E,
    PRV_CPSS_CH3_PORT_17_RES827_E,
    PRV_CPSS_CH3_PORT_17_RES828_E,
    PRV_CPSS_CH3_PORT_17_RES829_E,
    PRV_CPSS_CH3_PORT_17_RES830_E,
    PRV_CPSS_CH3_PORT_17_RES831_E,

    /* Port 18 Interrupt Cause Register */
    /* Indexes 832 - 863                */

    PRV_CPSS_CH3_PORT_18_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT18_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT18_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT18_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT18_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT18_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT18_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT18_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT18_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT18_E,
    PRV_CPSS_CH3_PORT_18_RES842_E,
    PRV_CPSS_CH3_PORT_18_RES843_E,
    PRV_CPSS_CH3_PORT_18_RES844_E,
    PRV_CPSS_CH3_PORT_18_RES845_E,
    PRV_CPSS_CH3_PORT_18_RES846_E,
    PRV_CPSS_CH3_PORT_18_RES847_E,
    PRV_CPSS_CH3_PORT_18_RES848_E,
    PRV_CPSS_CH3_PORT_18_RES849_E,
    PRV_CPSS_CH3_PORT_18_RES850_E,
    PRV_CPSS_CH3_PORT_18_RES851_E,
    PRV_CPSS_CH3_PORT_18_RES852_E,
    PRV_CPSS_CH3_PORT_18_RES853_E,
    PRV_CPSS_CH3_PORT_18_RES854_E,
    PRV_CPSS_CH3_PORT_18_RES855_E,
    PRV_CPSS_CH3_PORT_18_RES856_E,
    PRV_CPSS_CH3_PORT_18_RES857_E,
    PRV_CPSS_CH3_PORT_18_RES858_E,
    PRV_CPSS_CH3_PORT_18_RES859_E,
    PRV_CPSS_CH3_PORT_18_RES860_E,
    PRV_CPSS_CH3_PORT_18_RES861_E,
    PRV_CPSS_CH3_PORT_18_RES862_E,
    PRV_CPSS_CH3_PORT_18_RES863_E,

    /* Port 19 Interrupt Cause Register */
    /* Indexes 864 - 895                */

    PRV_CPSS_CH3_PORT_19_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT19_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT19_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT19_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT19_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT19_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT19_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT19_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT19_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT19_E,
    PRV_CPSS_CH3_PORT_19_RES874_E,
    PRV_CPSS_CH3_PORT_19_RES875_E,
    PRV_CPSS_CH3_PORT_19_RES876_E,
    PRV_CPSS_CH3_PORT_19_RES877_E,
    PRV_CPSS_CH3_PORT_19_RES878_E,
    PRV_CPSS_CH3_PORT_19_RES879_E,
    PRV_CPSS_CH3_PORT_19_RES880_E,
    PRV_CPSS_CH3_PORT_19_RES881_E,
    PRV_CPSS_CH3_PORT_19_RES882_E,
    PRV_CPSS_CH3_PORT_19_RES883_E,
    PRV_CPSS_CH3_PORT_19_RES884_E,
    PRV_CPSS_CH3_PORT_19_RES885_E,
    PRV_CPSS_CH3_PORT_19_RES886_E,
    PRV_CPSS_CH3_PORT_19_RES887_E,
    PRV_CPSS_CH3_PORT_19_RES888_E,
    PRV_CPSS_CH3_PORT_19_RES889_E,
    PRV_CPSS_CH3_PORT_19_RES890_E,
    PRV_CPSS_CH3_PORT_19_RES891_E,
    PRV_CPSS_CH3_PORT_19_RES892_E,
    PRV_CPSS_CH3_PORT_19_RES893_E,
    PRV_CPSS_CH3_PORT_19_RES894_E,
    PRV_CPSS_CH3_PORT_19_RES895_E,

    /* Port 20 Interrupt Cause Register */
    /* Indexes 896 - 927                */

    PRV_CPSS_CH3_PORT_20_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT20_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT20_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT20_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT20_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT20_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT20_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT20_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT20_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT20_E,
    PRV_CPSS_CH3_PORT_20_RES906_E,
    PRV_CPSS_CH3_PORT_20_RES907_E,
    PRV_CPSS_CH3_PORT_20_RES908_E,
    PRV_CPSS_CH3_PORT_20_RES909_E,
    PRV_CPSS_CH3_PORT_20_RES910_E,
    PRV_CPSS_CH3_PORT_20_RES911_E,
    PRV_CPSS_CH3_PORT_20_RES912_E,
    PRV_CPSS_CH3_PORT_20_RES913_E,
    PRV_CPSS_CH3_PORT_20_RES914_E,
    PRV_CPSS_CH3_PORT_20_RES915_E,
    PRV_CPSS_CH3_PORT_20_RES916_E,
    PRV_CPSS_CH3_PORT_20_RES917_E,
    PRV_CPSS_CH3_PORT_20_RES918_E,
    PRV_CPSS_CH3_PORT_20_RES919_E,
    PRV_CPSS_CH3_PORT_20_RES920_E,
    PRV_CPSS_CH3_PORT_20_RES921_E,
    PRV_CPSS_CH3_PORT_20_RES922_E,
    PRV_CPSS_CH3_PORT_20_RES923_E,
    PRV_CPSS_CH3_PORT_20_RES924_E,
    PRV_CPSS_CH3_PORT_20_RES925_E,
    PRV_CPSS_CH3_PORT_20_RES926_E,
    PRV_CPSS_CH3_PORT_20_RES927_E,

    /* Port 21 Interrupt Cause Register */
    /* Indexes 928 - 959                */

    PRV_CPSS_CH3_PORT_21_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT21_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT21_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT21_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT21_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT21_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT21_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT21_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT21_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT21_E,
    PRV_CPSS_CH3_PORT_21_RES938_E,
    PRV_CPSS_CH3_PORT_21_RES939_E,
    PRV_CPSS_CH3_PORT_21_RES940_E,
    PRV_CPSS_CH3_PORT_21_RES941_E,
    PRV_CPSS_CH3_PORT_21_RES942_E,
    PRV_CPSS_CH3_PORT_21_RES943_E,
    PRV_CPSS_CH3_PORT_21_RES944_E,
    PRV_CPSS_CH3_PORT_21_RES945_E,
    PRV_CPSS_CH3_PORT_21_RES946_E,
    PRV_CPSS_CH3_PORT_21_RES947_E,
    PRV_CPSS_CH3_PORT_21_RES948_E,
    PRV_CPSS_CH3_PORT_21_RES949_E,
    PRV_CPSS_CH3_PORT_21_RES950_E,
    PRV_CPSS_CH3_PORT_21_RES951_E,
    PRV_CPSS_CH3_PORT_21_RES952_E,
    PRV_CPSS_CH3_PORT_21_RES953_E,
    PRV_CPSS_CH3_PORT_21_RES954_E,
    PRV_CPSS_CH3_PORT_21_RES955_E,
    PRV_CPSS_CH3_PORT_21_RES956_E,
    PRV_CPSS_CH3_PORT_21_RES957_E,
    PRV_CPSS_CH3_PORT_21_RES958_E,
    PRV_CPSS_CH3_PORT_21_RES959_E,

    /* Port 22 Interrupt Cause Register */
    /* Indexes 960 - 991                */

    PRV_CPSS_CH3_PORT_22_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT22_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT22_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT22_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT22_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT22_E,
    PRV_CPSS_CH3_PORT_22_RES970_E,
    PRV_CPSS_CH3_PORT_22_RES971_E,
    PRV_CPSS_CH3_PORT_22_RES972_E,
    PRV_CPSS_CH3_PORT_22_RES973_E,
    PRV_CPSS_CH3_PORT_22_RES974_E,
    PRV_CPSS_CH3_PORT_22_RES975_E,
    PRV_CPSS_CH3_PORT_22_RES976_E,
    PRV_CPSS_CH3_PORT_22_RES977_E,
    PRV_CPSS_CH3_PORT_22_RES978_E,
    PRV_CPSS_CH3_PORT_22_RES979_E,
    PRV_CPSS_CH3_PORT_22_RES980_E,
    PRV_CPSS_CH3_PORT_22_RES981_E,
    PRV_CPSS_CH3_PORT_22_RES982_E,
    PRV_CPSS_CH3_PORT_22_RES983_E,
    PRV_CPSS_CH3_PORT_22_RES984_E,
    PRV_CPSS_CH3_PORT_22_RES985_E,
    PRV_CPSS_CH3_PORT_22_RES986_E,
    PRV_CPSS_CH3_PORT_22_RES987_E,
    PRV_CPSS_CH3_PORT_22_RES988_E,
    PRV_CPSS_CH3_PORT_22_RES989_E,
    PRV_CPSS_CH3_PORT_22_RES990_E,
    PRV_CPSS_CH3_PORT_22_RES991_E,

    /* Port 23 Interrupt Cause Register */
    /* Indexes 992 - 1023               */

    PRV_CPSS_CH3_PORT_23_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT23_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT23_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT23_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT23_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT23_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT23_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT23_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT23_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT23_E,
    PRV_CPSS_CH3_PORT_23_RES1002_E,
    PRV_CPSS_CH3_PORT_23_RES1003_E,
    PRV_CPSS_CH3_PORT_23_RES1004_E,
    PRV_CPSS_CH3_PORT_23_RES1005_E,
    PRV_CPSS_CH3_PORT_23_RES1006_E,
    PRV_CPSS_CH3_PORT_23_RES1007_E,
    PRV_CPSS_CH3_PORT_23_RES1008_E,
    PRV_CPSS_CH3_PORT_23_RES1009_E,
    PRV_CPSS_CH3_PORT_23_RES1010_E,
    PRV_CPSS_CH3_PORT_23_RES1011_E,
    PRV_CPSS_CH3_PORT_23_RES1012_E,
    PRV_CPSS_CH3_PORT_23_RES1013_E,
    PRV_CPSS_CH3_PORT_23_RES1014_E,
    PRV_CPSS_CH3_PORT_23_RES1015_E,
    PRV_CPSS_CH3_PORT_23_RES1016_E,
    PRV_CPSS_CH3_PORT_23_RES1017_E,
    PRV_CPSS_CH3_PORT_23_RES1018_E,
    PRV_CPSS_CH3_PORT_23_RES1019_E,
    PRV_CPSS_CH3_PORT_23_RES1020_E,
    PRV_CPSS_CH3_PORT_23_RES1021_E,
    PRV_CPSS_CH3_PORT_23_RES1022_E,
    PRV_CPSS_CH3_PORT_23_RES1023_E,

    /* CPU Port 63 Interrupt Cause Register */
    /* Indexes 1024 - 1055                  */

    PRV_CPSS_CH3_PORT_CPU_SUM_E,
    PRV_CPSS_CH3_LINK_STATUS_CHANGED_PORT_CPU_63_E,
    PRV_CPSS_CH3_AN_COMPLETED_PORT_CPU_63_E,
    PRV_CPSS_CH3_RX_FIFO_OVERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH3_TX_UNDERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH3_ADDRESS_OUT_OF_RANGE_PORT_CPU_63_E,
    PRV_CPSS_CH3_SYNC_STATUS_CHANGED_PORT_CPU_63_E,
    PRV_CPSS_CH3_PRBS_ERROR_PORT_CPU_63_E,
    PRV_CPSS_CH3_TX_FIFO_OVERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH3_TX_FIFO_UNDERRUN_PORT_CPU_63_E,
    PRV_CPSS_CH3_PORT_CPU_RES1034_E,
    PRV_CPSS_CH3_PORT_CPU_RES1035_E,
    PRV_CPSS_CH3_PORT_CPU_RES1036_E,
    PRV_CPSS_CH3_PORT_CPU_RES1037_E,
    PRV_CPSS_CH3_PORT_CPU_RES1038_E,
    PRV_CPSS_CH3_PORT_CPU_RES1039_E,
    PRV_CPSS_CH3_PORT_CPU_RES1040_E,
    PRV_CPSS_CH3_PORT_CPU_RES1041_E,
    PRV_CPSS_CH3_PORT_CPU_RES1042_E,
    PRV_CPSS_CH3_PORT_CPU_RES1043_E,
    PRV_CPSS_CH3_PORT_CPU_RES1044_E,
    PRV_CPSS_CH3_PORT_CPU_RES1045_E,
    PRV_CPSS_CH3_PORT_CPU_RES1046_E,
    PRV_CPSS_CH3_PORT_CPU_RES1047_E,
    PRV_CPSS_CH3_PORT_CPU_RES1048_E,
    PRV_CPSS_CH3_PORT_CPU_RES1049_E,
    PRV_CPSS_CH3_PORT_CPU_RES1050_E,
    PRV_CPSS_CH3_PORT_CPU_RES1051_E,
    PRV_CPSS_CH3_PORT_CPU_RES1052_E,
    PRV_CPSS_CH3_PORT_CPU_RES1053_E,
    PRV_CPSS_CH3_PORT_CPU_RES1054_E,
    PRV_CPSS_CH3_PORT_CPU_RES1055_E,

    /* Hyper.GStack Ports MIB Counters Interrupt Cause Register */
    /* Indexes 1056 - 1087                                      */

    PRV_CPSS_CH3_HGSMIB_SUM_E,
    PRV_CPSS_CH3_HGSMIB_PORT_24_COUNTER_WRAP_E,
    PRV_CPSS_CH3_HGSMIB_PORT_25_COUNTER_WRAP_E,
    PRV_CPSS_CH3_HGSMIB_PORT_26_COUNTER_WRAP_E,
    PRV_CPSS_CH3_HGSMIB_PORT_24_MIB_CAPTURE_E,
    PRV_CPSS_CH3_HGSMIB_PORT_25_MIB_CAPTURE_E,
    PRV_CPSS_CH3_HGSMIB_PORT_26_MIB_CAPTURE_E,
    PRV_CPSS_CH3_HGSMIB_PORT_27_COUNTER_WRAP_E,
    PRV_CPSS_CH3_HGSMIB_PORT_27_MIB_CAPTURE_E,
    PRV_CPSS_CH3_HGSMIB_RES1165_E,
    PRV_CPSS_CH3_HGSMIB_XSMI_WRITE_E,
    PRV_CPSS_CH3_HGSMIB_RES1067_E,
    PRV_CPSS_CH3_HGSMIB_RES1068_E,
    PRV_CPSS_CH3_HGSMIB_RES1069_E,
    PRV_CPSS_CH3_HGSMIB_RES1070_E,
    PRV_CPSS_CH3_HGSMIB_RES1071_E,
    PRV_CPSS_CH3_HGSMIB_RES1072_E,
    PRV_CPSS_CH3_HGSMIB_RES1073_E,
    PRV_CPSS_CH3_HGSMIB_RES1074_E,
    PRV_CPSS_CH3_HGSMIB_RES1075_E,
    PRV_CPSS_CH3_HGSMIB_RES1076_E,
    PRV_CPSS_CH3_HGSMIB_RES1077_E,
    PRV_CPSS_CH3_HGSMIB_RES1078_E,
    PRV_CPSS_CH3_HGSMIB_RES1079_E,
    PRV_CPSS_CH3_HGSMIB_RES1080_E,
    PRV_CPSS_CH3_HGSMIB_RES1081_E,
    PRV_CPSS_CH3_HGSMIB_RES1082_E,
    PRV_CPSS_CH3_HGSMIB_RES1083_E,
    PRV_CPSS_CH3_HGSMIB_RES1084_E,
    PRV_CPSS_CH3_HGSMIB_RES1085_E,
    PRV_CPSS_CH3_HGSMIB_RES1086_E,
    PRV_CPSS_CH3_HGSMIB_RES1087_E,

    /* XG Port 4 Interrupt Cause Register */
    /* Indexes 1088 - 1119                           */

    PRV_CPSS_CH3_XG_PORT_4_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT4_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT4_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT4_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT4_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1096_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT4_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT4_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT4_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1100_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1101_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1102_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1103_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1104_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1105_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1106_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1107_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1108_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1109_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1110_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1111_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1112_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1113_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1114_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1115_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1116_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1117_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1118_E,
    PRV_CPSS_CH3_XG_PORT_4_RES1119_E,

    /* XG Port 10 Interrupt Cause Register */
    /* Indexes 1120 - 1151                           */

    PRV_CPSS_CH3_XG_PORT_10_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT10_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT10_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT10_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT10_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1128_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT10_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT10_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT10_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1132_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1133_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1134_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1135_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1136_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1137_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1138_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1139_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1140_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1141_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1142_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1143_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1144_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1145_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1146_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1147_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1148_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1149_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1150_E,
    PRV_CPSS_CH3_XG_PORT_10_RES1151_E,

    /* XG Port 12 Interrupt Cause Register */
    /* Indexes 1152 - 1183                           */

    PRV_CPSS_CH3_XG_PORT_12_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT12_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT12_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT12_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT12_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1160_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT12_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT12_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT12_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1164_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1165_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1166_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1167_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1168_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1169_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1170_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1171_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1172_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1173_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1174_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1175_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1176_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1177_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1178_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1179_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1180_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1181_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1182_E,
    PRV_CPSS_CH3_XG_PORT_12_RES1183_E,

    /* XG Port 16 Interrupt Cause Register */
    /* Indexes 1184 - 1215                                      */

    PRV_CPSS_CH3_XG_PORT_16_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT16_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT16_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT16_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT16_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1192_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT16_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT16_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT16_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1196_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1197_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1198_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1199_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1200_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1201_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1202_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1203_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1204_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1205_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1206_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1207_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1208_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1209_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1210_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1211_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1212_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1213_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1214_E,
    PRV_CPSS_CH3_XG_PORT_16_RES1215_E,

    /* XG Port 22 Interrupt Cause Register */
    /* Indexes 1216 - 1247                 */

    PRV_CPSS_CH3_XG_PORT_22_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT22_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT22_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT22_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT22_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1224_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT22_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT22_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT22_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1228_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1229_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1230_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1231_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1232_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1233_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1234_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1235_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1236_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1237_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1238_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1239_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1240_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1241_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1242_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1243_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1244_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1245_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1246_E,
    PRV_CPSS_CH3_XG_PORT_22_RES1247_E,

    /* XG Port 24 Interrupt Cause Register */
    /* Indexes 1248 - 1279                 */

    PRV_CPSS_CH3_XG_PORT_24_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT24_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT24_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT24_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT24_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT24_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT24_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT24_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1256_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT24_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT24_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT24_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1260_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1261_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1262_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1263_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1264_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1265_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1266_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1267_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1268_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1269_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1270_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1271_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1272_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1273_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1274_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1275_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1276_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1277_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1278_E,
    PRV_CPSS_CH3_XG_PORT_24_RES1279_E,

    /* XG Port 25 Interrupt Cause Register */
    /* Indexes 1280 - 1311                 */

    PRV_CPSS_CH3_XG_PORT_25_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT25_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT25_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT25_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT25_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT25_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1288_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT25_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT25_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT25_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1292_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1293_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1294_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1295_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1296_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1297_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1298_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1299_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1300_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1301_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1302_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1303_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1304_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1305_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1306_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1307_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1308_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1309_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1310_E,
    PRV_CPSS_CH3_XG_PORT_25_RES1311_E,

    /* XG Port 26 Interrupt Cause Register */
    /* Indexes 1312 - 1343                 */

    PRV_CPSS_CH3_XG_PORT_26_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT26_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT26_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT26_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT26_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT26_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1320_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT26_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT26_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT26_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1324_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1325_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1326_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1327_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1328_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1329_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1330_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1331_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1332_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1333_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1334_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1335_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1336_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1337_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1338_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1339_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1340_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1341_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1342_E,
    PRV_CPSS_CH3_XG_PORT_26_RES1343_E,

    /* XG Port 27 Interrupt Cause Register */
    /* Indexes 1344 - 1375                 */

    PRV_CPSS_CH3_XG_PORT_27_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT27_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT27_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT27_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT27_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT27_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT27_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT27_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1352_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT27_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT27_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT27_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1356_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1357_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1358_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1359_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1360_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1361_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1362_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1363_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1364_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1365_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1366_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1367_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1368_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1369_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1370_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1371_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1372_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1373_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1374_E,
    PRV_CPSS_CH3_XG_PORT_27_RES1375_E,

    /* XG Port 0 Interrupt Cause Register */
    /* Indexes 1376 - 1407                 */

    PRV_CPSS_CH3_XG_PORT_0_SUM_E,
    PRV_CPSS_CH3_XG_LINK_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH3_XG_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_CH3_XG_TX_UNDERRUN_PORT0_E,
    PRV_CPSS_CH3_XG_FC_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_CH3_XG_ILLEGAL_SEQUENCE_PORT0_E,
    PRV_CPSS_CH3_XG_FAULT_TYPE_CHANGE_PORT0_E,
    PRV_CPSS_CH3_XG_ADDRESS_OUT_OF_RANGE_PORT0_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1384_E,
    PRV_CPSS_CH3_XG_NO_BUFF_PACKET_DROP_PORT0_E,
    PRV_CPSS_CH3_XG_COUNT_COPY_DONE_PORT0_E,
    PRV_CPSS_CH3_XG_COUNT_EXPIRED_PORT0_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1388_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1389_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1390_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1391_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1392_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1393_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1394_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1395_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1396_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1397_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1398_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1399_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1400_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1401_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1402_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1403_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1404_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1405_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1406_E,
    PRV_CPSS_CH3_XG_PORT_0_RES1407_E,

    /* Policy Engine Interrupt Cause Register */
    /* Indexes 1408 - 1439                    */

    PRV_CPSS_CH3_PCL_SUM_E,
    PRV_CPSS_CH3_PCL_ADDR_OUT_RANGE_E,
    PRV_CPSS_CH3_PCL_LOOKUP_LATENCY_FIFO_FULL_E,
    PRV_CPSS_CH3_PCL_LOOKUP_0_LATENCY_FIFO_FULL_E,
    PRV_CPSS_CH3_PCL_LOOKUP_1_LATENCY_FIFO_FULL_E,
    PRV_CPSS_CH3_PCL_LOOKUP_01_LATENCY_FIFO_FULL_E,
    PRV_CPSS_CH3_PCL_TCC_ECC_ERR_E,
    PRV_CPSS_CH3_PCL_RES1415_E,
    PRV_CPSS_CH3_PCL_RES1416_E,
    PRV_CPSS_CH3_PCL_RES1417_E,
    PRV_CPSS_CH3_PCL_RES1418_E,
    PRV_CPSS_CH3_PCL_RES1419_E,
    PRV_CPSS_CH3_PCL_RES1420_E,
    PRV_CPSS_CH3_PCL_RES1421_E,
    PRV_CPSS_CH3_PCL_RES1422_E,
    PRV_CPSS_CH3_PCL_RES1423_E,
    PRV_CPSS_CH3_PCL_RES1424_E,
    PRV_CPSS_CH3_PCL_RES1425_E,
    PRV_CPSS_CH3_PCL_RES1426_E,
    PRV_CPSS_CH3_PCL_RES1427_E,
    PRV_CPSS_CH3_PCL_RES1428_E,
    PRV_CPSS_CH3_PCL_RES1429_E,
    PRV_CPSS_CH3_PCL_RES1430_E,
    PRV_CPSS_CH3_PCL_RES1431_E,
    PRV_CPSS_CH3_PCL_RES1432_E,
    PRV_CPSS_CH3_PCL_RES1433_E,
    PRV_CPSS_CH3_PCL_RES1434_E,
    PRV_CPSS_CH3_PCL_RES1435_E,
    PRV_CPSS_CH3_PCL_RES1436_E,
    PRV_CPSS_CH3_PCL_RES1437_E,
    PRV_CPSS_CH3_PCL_RES1438_E,
    PRV_CPSS_CH3_PCL_RES1439_E,

    /* Bridge Engine Interrupt Cause Register */
    /* Indexes 1440 - 1471                    */

    PRV_CPSS_CH3_BRIDGE_SUM_E,
    PRV_CPSS_CH3_EB_NA_FIFO_FULL_E,
    PRV_CPSS_CH3_BRIDGE_ADDR_OUT_RANGE_E,
    PRV_CPSS_CH3_EB_TCC_E,
    PRV_CPSS_CH3_BRIDGE_RES1444_E,
    PRV_CPSS_CH3_BRIDGE_RES1445_E,
    PRV_CPSS_CH3_BRIDGE_RES1446_E,
    PRV_CPSS_CH3_BRIDGE_RES1447_E,
    PRV_CPSS_CH3_BRIDGE_RES1448_E,
    PRV_CPSS_CH3_BRIDGE_RES1449_E,
    PRV_CPSS_CH3_BRIDGE_RES1450_E,
    PRV_CPSS_CH3_BRIDGE_RES1451_E,
    PRV_CPSS_CH3_BRIDGE_RES1452_E,
    PRV_CPSS_CH3_BRIDGE_RES1453_E,
    PRV_CPSS_CH3_BRIDGE_RES1454_E,
    PRV_CPSS_CH3_BRIDGE_RES1455_E,
    PRV_CPSS_CH3_BRIDGE_RES1456_E,
    PRV_CPSS_CH3_BRIDGE_RES1457_E,
    PRV_CPSS_CH3_BRIDGE_RES1458_E,
    PRV_CPSS_CH3_BRIDGE_RES1459_E,
    PRV_CPSS_CH3_BRIDGE_RES1460_E,
    PRV_CPSS_CH3_BRIDGE_RES1461_E,
    PRV_CPSS_CH3_BRIDGE_RES1462_E,
    PRV_CPSS_CH3_BRIDGE_RES1463_E,
    PRV_CPSS_CH3_BRIDGE_RES1464_E,
    PRV_CPSS_CH3_BRIDGE_RES1465_E,
    PRV_CPSS_CH3_BRIDGE_RES1466_E,
    PRV_CPSS_CH3_BRIDGE_RES1467_E,
    PRV_CPSS_CH3_EB_SECURITY_BREACH_UPDATE_E,
    PRV_CPSS_CH3_BRIDGE_RES1469_E,
    PRV_CPSS_CH3_BRIDGE_RES1470_E,
    PRV_CPSS_CH3_BRIDGE_RES1471_E,

    /* Pre-Egress Interrupt Summary Register */
    /* Indexes 1472 - 1503                   */

    PRV_CPSS_CH3_PREEGR_SUM_E,
    PRV_CPSS_CH3_PREEGR_INGR_STC_SUM_E,
    PRV_CPSS_CH3_PREEGR_SCT_RATE_LIM_SUM_E,
    PRV_CPSS_CH3_PREEGR_RES1475_E,
    PRV_CPSS_CH3_PREEGR_RES1476_E,
    PRV_CPSS_CH3_PREEGR_RES1477_E,
    PRV_CPSS_CH3_PREEGR_RES1478_E,
    PRV_CPSS_CH3_PREEGR_RES1479_E,
    PRV_CPSS_CH3_PREEGR_RES1480_E,
    PRV_CPSS_CH3_PREEGR_RES1481_E,
    PRV_CPSS_CH3_PREEGR_RES1482_E,
    PRV_CPSS_CH3_PREEGR_RES1483_E,
    PRV_CPSS_CH3_PREEGR_RES1484_E,
    PRV_CPSS_CH3_PREEGR_RES1485_E,
    PRV_CPSS_CH3_PREEGR_RES1486_E,
    PRV_CPSS_CH3_PREEGR_RES1487_E,
    PRV_CPSS_CH3_PREEGR_RES1488_E,
    PRV_CPSS_CH3_PREEGR_RES1489_E,
    PRV_CPSS_CH3_PREEGR_RES1490_E,
    PRV_CPSS_CH3_PREEGR_RES1491_E,
    PRV_CPSS_CH3_PREEGR_RES1492_E,
    PRV_CPSS_CH3_PREEGR_RES1493_E,
    PRV_CPSS_CH3_PREEGR_RES1494_E,
    PRV_CPSS_CH3_PREEGR_RES1495_E,
    PRV_CPSS_CH3_PREEGR_RES1496_E,
    PRV_CPSS_CH3_PREEGR_RES1497_E,
    PRV_CPSS_CH3_PREEGR_RES1498_E,
    PRV_CPSS_CH3_PREEGR_RES1499_E,
    PRV_CPSS_CH3_PREEGR_RES1500_E,
    PRV_CPSS_CH3_PREEGR_RES1501_E,
    PRV_CPSS_CH3_PREEGR_RES1502_E,
    PRV_CPSS_CH3_PREEGR_RES1503_E,

    /* SCT Rate Limiters Interrupt Cause Register */
    /* Indexes 1504 - 1535                        */

    PRV_CPSS_CH3_SCT_RATE_LIMITER_SUM_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_1_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_2_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_3_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_4_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_5_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_6_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_7_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_8_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_9_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_10_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_11_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_12_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_13_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_14_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_15_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_16_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_17_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_18_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_19_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_20_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_21_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_22_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_23_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_24_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_25_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_26_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_27_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_28_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_29_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_30_PKT_DROP_E,
    PRV_CPSS_CH3_SCT_RATE_LIMITER_31_PKT_DROP_E,


    /* Ingress STC (Sampling To CPU) Interrupt Cause Register */
    /* Indexes 1536 - 1567                                    */

    PRV_CPSS_CH3_INGRESS_STC_SUM_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT0_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT1_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT2_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT3_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT4_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT5_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT6_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT7_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT8_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT9_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT10_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT11_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT12_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT13_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT14_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT15_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT16_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT17_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT18_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT19_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT20_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT21_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT22_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT23_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT24_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT25_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT26_E,
    PRV_CPSS_CH3_MAC_SFLOW_PORT27_E,
    PRV_CPSS_CH3_INGRESS_STC_RES1565_E,
    PRV_CPSS_CH3_INGRESS_STC_RES1566_E,
    PRV_CPSS_CH3_INGRESS_STC_RES1567_E,


    /* Transmit Queue Interrupt Summary Cause Register */
    /* Indexes 1568 - 1599                             */

    PRV_CPSS_CH3_TXQ_SUM_E,
    PRV_CPSS_CH3_TXQ_SUM_WATCHDOG_E,
    PRV_CPSS_CH3_TXQ_SUM_FLASH_E,
    PRV_CPSS_CH3_TXQ_SUM_GENERAL_E,
    PRV_CPSS_CH3_TXQ_SUM_GPP_E,
    PRV_CPSS_CH3_TXQ_SUM_EGRESS_STC_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1574_E,
    PRV_CPSS_CH3_TXQ_SUM_FULL_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1576_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1577_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1578_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1579_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1580_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1581_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1582_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1583_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1584_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1585_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1586_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1587_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1588_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1589_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1590_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1591_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1592_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1593_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1594_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1595_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1596_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1597_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1598_E,
    PRV_CPSS_CH3_TXQ_SUM_RES1599_E,

    /* Transmit Queue Flush Done Interrupt Cause Register */
    /* Indexes 1600 - 1631                                */

    PRV_CPSS_CH3_TXQ_FLASH_SUM_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT0_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT1_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT2_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT3_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT4_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT5_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT6_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT7_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT8_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT9_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT10_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT11_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT12_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT13_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT14_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT15_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT16_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT17_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT18_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT19_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT20_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT21_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT22_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT23_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT24_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT25_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT26_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT27_E,
    PRV_CPSS_CH3_TQ_TXQ2_FLUSH_PORT_CPU_63_E,
    PRV_CPSS_CH3_TXQ_FLASH_RES1630_E,
    PRV_CPSS_CH3_TXQ_FLASH_RES1631_E,


    /* Transmit Queue WatchDog Interrupt Cause Register */
    /* Indexes 1632 - 1663                              */

    PRV_CPSS_CH3_TXQ_WATCHDOG_SUM_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT0_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT1_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT2_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT3_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT4_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT5_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT6_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT7_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT8_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT9_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT10_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT11_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT12_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT13_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT14_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT15_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT16_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT17_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT18_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT19_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT20_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT21_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT22_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT23_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT24_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT25_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT26_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT27_E,
    PRV_CPSS_CH3_TQ_WATCHDOG_EX_PORT_CPU_63_E,
    PRV_CPSS_CH3_TXQ_WATCHDOG_RES1662_E,
    PRV_CPSS_CH3_TXQ_WATCHDOG_RES1663_E,


    /* Transmit Queue General Interrupt Cause Register */
    /* Indexes 1664 - 1695                             */

    PRV_CPSS_CH3_TXQ_GEN_SUM_E,
    PRV_CPSS_CH3_TQ_SNIFF_DESC_DROP_E,
    PRV_CPSS_CH3_TXQ_GEN_BAD_ADDR_E,
    PRV_CPSS_CH3_TXQ_GEN_DESC_FULL_E,
    PRV_CPSS_CH3_TXQ_GEN_PARITY_ERR_DESC_MEM_E,
    PRV_CPSS_CH3_TXQ_GEN_PARITY_ERR_PTR_MEM_E,
    PRV_CPSS_CH3_TQ_TOTAL_DESC_UNDERFLOW_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1671_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1672_E,
    PRV_CPSS_CH3_TQ_TOTAL_BUFF_UNDERFLOW_E,
    PRV_CPSS_CH3_TXQ_GEN_BUF_FULL_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1675_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1676_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1677_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1678_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1679_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1680_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1681_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1682_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1683_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1684_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1685_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1686_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1687_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1688_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1689_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1690_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1691_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1692_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1693_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1694_E,
    PRV_CPSS_CH3_TXQ_GEN_RES1695_E,

    /* Transmit Queue Full Interrupt Cause register */
    /* Indexes 1696 - 1727                          */

    PRV_CPSS_CH3_TXQ_FULL_SUM_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT0_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT1_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT2_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT3_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT4_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT5_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT6_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT7_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT8_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT9_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT10_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT11_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT12_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT13_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT14_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT15_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT16_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT17_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT18_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT19_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT20_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT21_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT22_E,
    PRV_CPSS_CH3_TQ_DESC_FULL_PORT23_E,
    PRV_CPSS_CH3_TQ_FULL_XG_PORT24_E,
    PRV_CPSS_CH3_TQ_FULL_XG_PORT27_E,
    PRV_CPSS_CH3_TQ_GIGA_FIFO_FULL_E,
    PRV_CPSS_CH3_TQ_MC_DESC_FULL_E,
    PRV_CPSS_CH3_TQ_FULL_XG_PORT25_E,
    PRV_CPSS_CH3_TQ_FULL_XG_PORT26_E,
    PRV_CPSS_CH3_TQ_XG_MC_FIFO_FULL_E,

    /* Egress STC Interrupt Cause Register */
    /* Indexes 1728 - 1759                 */

    PRV_CPSS_CH3_EGRESS_STC_SUM_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT0_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT1_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT2_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT3_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT4_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT5_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT6_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT7_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT8_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT9_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT10_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT11_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT12_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT13_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT14_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT15_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT16_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT17_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT18_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT19_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT20_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT21_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT22_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT23_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT24_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT25_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT26_E,
    PRV_CPSS_CH3_EGRESS_STC_PORT27_E,
    PRV_CPSS_CH3_EGRESS_STC_RES1757_E,
    PRV_CPSS_CH3_EGRESS_STC_RES1758_E,
    PRV_CPSS_CH3_EGRESS_STC_RES1759_E,


    /* Buffer Memory Main Interrupt Cause Register */
    /* Indexes 1760 - 1791                         */

    PRV_CPSS_CH3_BUF_MEM_MAIN_SUM_E,
    PRV_CPSS_CH3_BM_MAIN_REG0_SUM_E,
    PRV_CPSS_CH3_BM_MAIN_REG1_SUM_E,
    PRV_CPSS_CH3_BM_MAIN_RES1763_E,
    PRV_CPSS_CH3_BM_MAIN_RES1764_E,
    PRV_CPSS_CH3_BM_MAIN_RES1765_E,
    PRV_CPSS_CH3_BM_MAIN_RES1766_E,
    PRV_CPSS_CH3_BM_MAIN_RES1767_E,
    PRV_CPSS_CH3_BM_MAIN_RES1768_E,
    PRV_CPSS_CH3_BM_MAIN_RES1769_E,
    PRV_CPSS_CH3_BM_MAIN_RES1770_E,
    PRV_CPSS_CH3_BM_MAIN_RES1771_E,
    PRV_CPSS_CH3_BM_MAIN_RES1772_E,
    PRV_CPSS_CH3_BM_MAIN_RES1773_E,
    PRV_CPSS_CH3_BM_MAIN_RES1774_E,
    PRV_CPSS_CH3_BM_MAIN_RES1775_E,
    PRV_CPSS_CH3_BM_MAIN_RES1776_E,
    PRV_CPSS_CH3_BM_MAIN_RES1777_E,
    PRV_CPSS_CH3_BM_MAIN_RES1778_E,
    PRV_CPSS_CH3_BM_MAIN_RES1779_E,
    PRV_CPSS_CH3_BM_MAIN_RES1780_E,
    PRV_CPSS_CH3_BM_MAIN_RES1781_E,
    PRV_CPSS_CH3_BM_MAIN_RES1782_E,
    PRV_CPSS_CH3_BM_MAIN_RES1783_E,
    PRV_CPSS_CH3_BM_MAIN_RES1784_E,
    PRV_CPSS_CH3_BM_MAIN_RES1785_E,
    PRV_CPSS_CH3_BM_MAIN_RES1786_E,
    PRV_CPSS_CH3_BM_MAIN_RES1787_E,
    PRV_CPSS_CH3_BM_MAIN_RES1788_E,
    PRV_CPSS_CH3_BM_MAIN_RES1789_E,
    PRV_CPSS_CH3_BM_MAIN_RES1790_E,
    PRV_CPSS_CH3_BM_MAIN_RES1791_E,

    /* Buffer Memory Interrupt Cause Register 0 */
    /* Indexes 1792 - 1823                      */

    PRV_CPSS_CH3_BUF_MEM_0_SUM_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT0_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT1_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT2_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT3_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT4_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT5_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT6_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT7_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT8_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT9_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT10_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT11_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT12_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT13_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT14_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT15_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT16_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT17_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT18_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT19_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT20_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT21_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT22_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT23_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT24_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT25_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT26_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT27_E,
    PRV_CPSS_CH3_BM_TX_FIFO_OVER_RUN_PORT28_E,
    PRV_CPSS_CH3_BUF_MEM_MAC_ERROR_E,
    PRV_CPSS_CH3_BUF_MEM_BURST_FIFO_OVER_RUN_E,

    /* Buffer Memory Interrupt Cause Register 1 */
    /* Indexes 1824 - 1855                      */

    PRV_CPSS_CH3_BUF_MEM_1_SUM_E,
    PRV_CPSS_CH3_BUF_MEM_BANK0_ONE_ECC_ERROR_E,
    PRV_CPSS_CH3_BUF_MEM_BANK0_TWO_OR_MORE_ECC_ERRORS_E,
    PRV_CPSS_CH3_BUF_MEM_BANK1_ONE_ECC_ERROR_E,
    PRV_CPSS_CH3_BUF_MEM_BANK1_TWO_OR_MORE_ECC_ERRORS_E,
    PRV_CPSS_CH3_BM_RES1829_E,
    PRV_CPSS_CH3_BM_RES1830_E,
    PRV_CPSS_CH3_BM_RES1831_E,
    PRV_CPSS_CH3_BM_RES1832_E,
    PRV_CPSS_CH3_BM_RES1833_E,
    PRV_CPSS_CH3_BM_RES1834_E,
    PRV_CPSS_CH3_BM_RES1835_E,
    PRV_CPSS_CH3_BM_RES1836_E,
    PRV_CPSS_CH3_BM_RES1837_E,
    PRV_CPSS_CH3_BM_RES1838_E,
    PRV_CPSS_CH3_BM_RES1839_E,
    PRV_CPSS_CH3_BM_RES1840_E,
    PRV_CPSS_CH3_BM_RES1841_E,
    PRV_CPSS_CH3_BM_RES1842_E,
    PRV_CPSS_CH3_BM_RES1843_E,
    PRV_CPSS_CH3_BM_RES1844_E,
    PRV_CPSS_CH3_BM_RES1845_E,
    PRV_CPSS_CH3_BM_RES1846_E,
    PRV_CPSS_CH3_BM_RES1847_E,
    PRV_CPSS_CH3_BM_RES1848_E,
    PRV_CPSS_CH3_BM_RES1849_E,
    PRV_CPSS_CH3_BM_RES1850_E,
    PRV_CPSS_CH3_BM_RES1851_E,
    PRV_CPSS_CH3_BM_RES1852_E,
    PRV_CPSS_CH3_BM_RES1853_E,
    PRV_CPSS_CH3_BM_RES1854_E,
    PRV_CPSS_CH3_BM_RES1855_E,

    /* Buffer Management Interrupt Cause Register 0 */
    /* Indexes 1856 - 1887                          */

    PRV_CPSS_CH3_BM_SUM0_E,
    PRV_CPSS_CH3_BM_EMPTY_CLEAR_E,
    PRV_CPSS_CH3_BM_AGED_PACKET_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_E,
    PRV_CPSS_CH3_BM_PORT_RX_BUFFERS_CNT_UNDERRUN_E,
    PRV_CPSS_CH3_BM_PORT_RX_BUFFERS_CNT_OVERRUN_E,
    PRV_CPSS_CH3_BM_GE_CNT_UNDERRUN_E,
    PRV_CPSS_CH3_BM_GE_CNT_OVERRUN_E,
    PRV_CPSS_CH3_BM_XG_CNT_UNDERRUN_E,
    PRV_CPSS_CH3_BM_XG_CNT_OVERRUN_E,
    PRV_CPSS_CH3_BM_GLOBAL_CNT_UNDERRUN_E,
    PRV_CPSS_CH3_BM_GLOBAL_CNT_OVERRUN_E,
    PRV_CPSS_CH3_BM_TRIGGER_AGING_DONE_E,
    PRV_CPSS_CH3_BM_LL_PORT1_PARITY_ERROR_E,
    PRV_CPSS_CH3_BM_LL_PORT2_PARITY_ERROR_E,
    PRV_CPSS_CH3_BM_CNRL_MEM_PARITY_ERROR_E,
    PRV_CPSS_CH3_BM_MC_CNT_PARITY_ERROR_E,
    PRV_CPSS_CH3_BM_WRONG_SRC_PORT_E,
    PRV_CPSS_CH3_BM_MC_INC_OVERFLOW_E,
    PRV_CPSS_CH3_BM_MC_INC_UNDERRUN_E,
    PRV_CPSS_CH3_BM_PORT_RX_FULL_E,
    PRV_CPSS_CH3_BM_RES1877_E,
    PRV_CPSS_CH3_BM_RES1878_E,
    PRV_CPSS_CH3_BM_RES1879_E,
    PRV_CPSS_CH3_BM_RES1880_E,
    PRV_CPSS_CH3_BM_RES1881_E,
    PRV_CPSS_CH3_BM_RES1882_E,
    PRV_CPSS_CH3_BM_RES1883_E,
    PRV_CPSS_CH3_BM_RES1884_E,
    PRV_CPSS_CH3_BM_RES1885_E,
    PRV_CPSS_CH3_BM_RES1886_E,
    PRV_CPSS_CH3_BM_RES1887_E,

    /* Buffer Management Interrupt Cause Register 1 */
    /* Indexes 1888 - 1919                          */

    PRV_CPSS_CH3_BM_SUM1_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT0_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT1_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT2_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT3_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT4_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT5_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT6_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT7_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT8_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT9_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT10_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT11_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT12_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT13_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT14_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT15_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT16_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT17_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT18_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT19_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT20_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT21_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT22_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT23_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT24_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT25_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT26_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT27_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_GIG_PORTS_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_HG_PORTS_E,
    PRV_CPSS_CH3_BM_MAX_BUFF_REACHED_PORT_CPU_63_E,


    /* MAC Table Interrupt Cause Register */
    /* Indexes 1920 - 1951                */

    PRV_CPSS_CH3_MAC_SUM_E,
    PRV_CPSS_CH3_MAC_NUM_OF_HOP_EXP_E,
    PRV_CPSS_CH3_MAC_NA_LEARNED_E,
    PRV_CPSS_CH3_MAC_NA_NOT_LEARNED_E,
    PRV_CPSS_CH3_MAC_AGE_VIA_TRIGGER_ENDED_E,
    PRV_CPSS_CH3_MAC_RES1925_E,
    PRV_CPSS_CH3_MAC_RES1926_E,
    PRV_CPSS_CH3_MAC_RES1927_E,
    PRV_CPSS_CH3_MAC_RES1928_E,
    PRV_CPSS_CH3_MAC_UPDATE_FROM_CPU_DONE_E,
    PRV_CPSS_CH3_MAC_MESSAGE_TO_CPU_READY_E,
    PRV_CPSS_CH3_MAC_RES1931_E,
    PRV_CPSS_CH3_MAC_NA_SELF_LEARNED_E,
    PRV_CPSS_CH3_MAC_NA_FROM_CPU_LEARNED_E,
    PRV_CPSS_CH3_MAC_NA_FROM_CPU_DROPPED_E,
    PRV_CPSS_CH3_MAC_AGED_OUT_E,
    PRV_CPSS_CH3_MAC_FIFO_2_CPU_EXCEEDED_E,
    PRV_CPSS_CH3_MAC_RES1937_E,
    PRV_CPSS_CH3_MAC_RES1938_E,
    PRV_CPSS_CH3_MAC_RES1939_E,
    PRV_CPSS_CH3_MAC_RES1940_E,
    PRV_CPSS_CH3_MAC_RES1941_E,
    PRV_CPSS_CH3_MAC_RES1942_E,
    PRV_CPSS_CH3_MAC_RES1943_E,
    PRV_CPSS_CH3_MAC_RES1944_E,
    PRV_CPSS_CH3_MAC_RES1945_E,
    PRV_CPSS_CH3_MAC_RES1946_E,
    PRV_CPSS_CH3_MAC_RES1947_E,
    PRV_CPSS_CH3_MAC_RES1948_E,
    PRV_CPSS_CH3_MAC_RES1949_E,
    PRV_CPSS_CH3_MAC_RES1950_E,
    PRV_CPSS_CH3_MAC_RES1951_E,

    /* GOP0  MIB  Interrupt Cause Register */
    /* Indexes 1952 - 1983                 */

    PRV_CPSS_CH3_GOP0_SUM_E,
    PRV_CPSS_CH3_GOP_ADDRESS_OUT_OF_RANGE_0_E,
    PRV_CPSS_CH3_GOP_COUNT_EXPIRED_0_E,
    PRV_CPSS_CH3_GOP_COUNT_COPY_DONE_0_E,
    PRV_CPSS_CH3_GOP0_RES1956_E,
    PRV_CPSS_CH3_GOP0_RES1957_E,
    PRV_CPSS_CH3_GOP0_RES1958_E,
    PRV_CPSS_CH3_GOP0_RES1959_E,
    PRV_CPSS_CH3_GOP0_RES1960_E,
    PRV_CPSS_CH3_GOP0_RES1961_E,
    PRV_CPSS_CH3_GOP0_RES1962_E,
    PRV_CPSS_CH3_GOP0_RES1963_E,
    PRV_CPSS_CH3_GOP0_RES1964_E,
    PRV_CPSS_CH3_GOP0_RES1965_E,
    PRV_CPSS_CH3_GOP0_RES1966_E,
    PRV_CPSS_CH3_GOP0_RES1967_E,
    PRV_CPSS_CH3_GOP0_RES1968_E,
    PRV_CPSS_CH3_GOP0_RES1969_E,
    PRV_CPSS_CH3_GOP0_RES1970_E,
    PRV_CPSS_CH3_GOP0_RES1971_E,
    PRV_CPSS_CH3_GOP0_RES1972_E,
    PRV_CPSS_CH3_GOP0_RES1973_E,
    PRV_CPSS_CH3_GOP0_RES1974_E,
    PRV_CPSS_CH3_GOP0_RES1975_E,
    PRV_CPSS_CH3_GOP0_RES1976_E,
    PRV_CPSS_CH3_GOP0_RES1977_E,
    PRV_CPSS_CH3_GOP0_RES1978_E,
    PRV_CPSS_CH3_GOP0_RES1979_E,
    PRV_CPSS_CH3_GOP0_RES1980_E,
    PRV_CPSS_CH3_GOP0_RES1981_E,
    PRV_CPSS_CH3_GOP0_RES1982_E,
    PRV_CPSS_CH3_GOP0_RES1983_E,

    /* GOP1  MIB  Interrupt Cause Register */
    /* Indexes 1984 - 2015                 */

    PRV_CPSS_CH3_GOP1_SUM_E,
    PRV_CPSS_CH3_GOP_ADDRESS_OUT_OF_RANGE_1_E,
    PRV_CPSS_CH3_GOP_COUNT_EXPIRED_1_E,
    PRV_CPSS_CH3_GOP_COUNT_COPY_DONE_1_E,
    PRV_CPSS_CH3_GOP1_RES1987_E,
    PRV_CPSS_CH3_GOP1_RES1988_E,
    PRV_CPSS_CH3_GOP1_RES1989_E,
    PRV_CPSS_CH3_GOP1_RES1990_E,
    PRV_CPSS_CH3_GOP1_RES1991_E,
    PRV_CPSS_CH3_GOP1_RES1992_E,
    PRV_CPSS_CH3_GOP1_RES1993_E,
    PRV_CPSS_CH3_GOP1_RES1994_E,
    PRV_CPSS_CH3_GOP1_RES1995_E,
    PRV_CPSS_CH3_GOP1_RES1996_E,
    PRV_CPSS_CH3_GOP1_RES1997_E,
    PRV_CPSS_CH3_GOP1_RES1998_E,
    PRV_CPSS_CH3_GOP1_RES1999_E,
    PRV_CPSS_CH3_GOP1_RES2000_E,
    PRV_CPSS_CH3_GOP1_RES2001_E,
    PRV_CPSS_CH3_GOP1_RES2002_E,
    PRV_CPSS_CH3_GOP1_RES2003_E,
    PRV_CPSS_CH3_GOP1_RES2004_E,
    PRV_CPSS_CH3_GOP1_RES2005_E,
    PRV_CPSS_CH3_GOP1_RES2006_E,
    PRV_CPSS_CH3_GOP1_RES2007_E,
    PRV_CPSS_CH3_GOP1_RES2008_E,
    PRV_CPSS_CH3_GOP1_RES2009_E,
    PRV_CPSS_CH3_GOP1_RES2010_E,
    PRV_CPSS_CH3_GOP1_RES2011_E,
    PRV_CPSS_CH3_GOP1_RES2012_E,
    PRV_CPSS_CH3_GOP1_RES2013_E,
    PRV_CPSS_CH3_GOP1_RES2014_E,


    /* GOP2  MIB  Interrupt Cause Register */
    /* Indexes 2016 - 2047                 */

    PRV_CPSS_CH3_GOP2_SUM_E,
    PRV_CPSS_CH3_GOP_ADDRESS_OUT_OF_RANGE_2_E,
    PRV_CPSS_CH3_GOP_COUNT_EXPIRED_2_E,
    PRV_CPSS_CH3_GOP_COUNT_COPY_DONE_2_E,
    PRV_CPSS_CH3_GOP2_RES2019_E,
    PRV_CPSS_CH3_GOP2_RES2020_E,
    PRV_CPSS_CH3_GOP2_RES2021_E,
    PRV_CPSS_CH3_GOP2_RES2022_E,
    PRV_CPSS_CH3_GOP2_RES2023_E,
    PRV_CPSS_CH3_GOP2_RES2024_E,
    PRV_CPSS_CH3_GOP2_RES2025_E,
    PRV_CPSS_CH3_GOP2_RES2026_E,
    PRV_CPSS_CH3_GOP2_RES2027_E,
    PRV_CPSS_CH3_GOP2_RES2028_E,
    PRV_CPSS_CH3_GOP2_RES2029_E,
    PRV_CPSS_CH3_GOP2_RES2030_E,
    PRV_CPSS_CH3_GOP2_RES2031_E,
    PRV_CPSS_CH3_GOP2_RES2032_E,
    PRV_CPSS_CH3_GOP2_RES2033_E,
    PRV_CPSS_CH3_GOP2_RES2034_E,
    PRV_CPSS_CH3_GOP2_RES2035_E,
    PRV_CPSS_CH3_GOP2_RES2036_E,
    PRV_CPSS_CH3_GOP2_RES2037_E,
    PRV_CPSS_CH3_GOP2_RES2038_E,
    PRV_CPSS_CH3_GOP2_RES2039_E,
    PRV_CPSS_CH3_GOP2_RES2040_E,
    PRV_CPSS_CH3_GOP2_RES2041_E,
    PRV_CPSS_CH3_GOP2_RES2042_E,
    PRV_CPSS_CH3_GOP2_RES2043_E,
    PRV_CPSS_CH3_GOP2_RES2044_E,
    PRV_CPSS_CH3_GOP2_RES2045_E,
    PRV_CPSS_CH3_GOP2_RES2046_E,

    /* Tri-Speed Ports GOP3 and XG MIBs  Interrupt Cause Register   */
    /* Indexes 2048 - 2079                                          */

    PRV_CPSS_CH3_GOP3_SUM_E,
    PRV_CPSS_CH3_GOP_ADDRESS_OUT_OF_RANGE_3_E,
    PRV_CPSS_CH3_GOP_COUNT_EXPIRED_3_E,
    PRV_CPSS_CH3_GOP_COUNT_COPY_DONE_3_E,
    PRV_CPSS_CH3_GOP3_RES2050_E,
    PRV_CPSS_CH3_GOP3_RES2051_E,
    PRV_CPSS_CH3_GOP3_RES2052_E,
    PRV_CPSS_CH3_GOP3_RES2053_E,
    PRV_CPSS_CH3_GOP3_RES2054_E,
    PRV_CPSS_CH3_GOP3_RES2055_E,
    PRV_CPSS_CH3_GOP3_RES2056_E,
    PRV_CPSS_CH3_GOP3_RES2057_E,
    PRV_CPSS_CH3_GOP3_RES2058_E,
    PRV_CPSS_CH3_GOP3_RES2059_E,
    PRV_CPSS_CH3_GOP3_RES2060_E,
    PRV_CPSS_CH3_GOP3_RES2061_E,
    PRV_CPSS_CH3_GOP3_RES2062_E,
    PRV_CPSS_CH3_GOP3_RES2063_E,
    PRV_CPSS_CH3_GOP3_RES2064_E,
    PRV_CPSS_CH3_GOP3_RES2065_E,
    PRV_CPSS_CH3_GOP3_RES2066_E,
    PRV_CPSS_CH3_GOP3_RES2067_E,
    PRV_CPSS_CH3_GOP3_RES2068_E,
    PRV_CPSS_CH3_GOP3_RES2069_E,
    PRV_CPSS_CH3_GOP3_RES2070_E,
    PRV_CPSS_CH3_GOP3_RES2071_E,
    PRV_CPSS_CH3_GOP3_RES2072_E,
    PRV_CPSS_CH3_GOP3_RES2073_E,
    PRV_CPSS_CH3_GOP3_RES2074_E,
    PRV_CPSS_CH3_GOP3_RES2075_E,
    PRV_CPSS_CH3_GOP3_RES2076_E,
    PRV_CPSS_CH3_GOP3_RES2077_E,

    /* CNC Interrupt Cause Register  */
    /* Indexes 2080 - 2111           */

    PRV_CPSS_CH3_CNC_SUM_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK0_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK1_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK2_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK3_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK4_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK5_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK6_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK7_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK8_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK9_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK10_E,
    PRV_CPSS_CH3_CNC_WRAPAROUND_BLOCK11_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK0_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK1_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK2_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK3_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK4_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK5_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK6_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK7_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK8_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK9_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK10_E,
    PRV_CPSS_CH3_CNC_RATELIMIT_FIFODROP_BLOCK11_E,
    PRV_CPSS_CH3_CNC_DUMP_FINISHED_E,
    PRV_CPSS_CH3_CNC_UPDATE_LOST_E,
    PRV_CPSS_CH3_GOP3_RES2105_E,
    PRV_CPSS_CH3_GOP3_RES2106_E,
    PRV_CPSS_CH3_GOP3_RES2107_E,
    PRV_CPSS_CH3_GOP3_RES2108_E,
    PRV_CPSS_CH3_GOP3_RES2109_E,

    /* XG Ports  Interrupt Cause Register */
    /* Indexes 2112 - 2143                */

    PRV_CPSS_CH3_XG_PORTS_SUM_E,
    PRV_CPSS_CH3_XG_RES2113_E,
    PRV_CPSS_CH3_XG_RES2114_E,
    PRV_CPSS_CH3_XG_RES2115_E,
    PRV_CPSS_CH3_XG_PORT4_SUM_E,
    PRV_CPSS_CH3_XG_RES2117_E,
    PRV_CPSS_CH3_XG_RES2118_E,
    PRV_CPSS_CH3_XG_RES2119_E,
    PRV_CPSS_CH3_XG_RES2120_E,
    PRV_CPSS_CH3_XG_RES2121_E,
    PRV_CPSS_CH3_XG_PORT10_SUM_E,
    PRV_CPSS_CH3_XG_RES2123_E,
    PRV_CPSS_CH3_XG_PORT12_SUM_E,
    PRV_CPSS_CH3_XG_RES2125_E,
    PRV_CPSS_CH3_XG_RES2126_E,
    PRV_CPSS_CH3_XG_RES2127_E,
    PRV_CPSS_CH3_XG_PORT16_SUM_E,
    PRV_CPSS_CH3_XG_RES2128_E,
    PRV_CPSS_CH3_XG_RES2129_E,
    PRV_CPSS_CH3_XG_RES2130_E,
    PRV_CPSS_CH3_XG_RES2131_E,
    PRV_CPSS_CH3_XG_RES2132_E,
    PRV_CPSS_CH3_XG_PORT22_SUM_E,
    PRV_CPSS_CH3_XG_RES2134_E,
    PRV_CPSS_CH3_XG_PORT24_SUM_E,
    PRV_CPSS_CH3_XG_PORT25_SUM_E,
    PRV_CPSS_CH3_XG_PORT26_SUM_E,
    PRV_CPSS_CH3_XG_PORT27_SUM_E,
    PRV_CPSS_CH3_XG_RES2139_E,
    PRV_CPSS_CH3_XG_RES2140_E,
    PRV_CPSS_CH3_XG_RES2141_E,
    PRV_CPSS_CH3_XG_PORT0_SUM_E,


    /* Ingress Policer (PLR) Interrupt Cause Register   */
    /* Indexes 2144 - 2175                              */

    PRV_CPSS_CH3_POLICER_SUM_E,
    PRV_CPSS_CH3_POLICER_DATA_ERR_E,
    PRV_CPSS_CH3_POLICER_ADDR_OUT_OF_MEMORY_E,
    PRV_CPSS_CH3_POLICER_RES2145_E,
    PRV_CPSS_CH3_POLICER_RES2146_E,
    PRV_CPSS_CH3_POLICER_RES2147_E,
    PRV_CPSS_CH3_POLICER_RES2148_E,
    PRV_CPSS_CH3_POLICER_RES2149_E,
    PRV_CPSS_CH3_POLICER_RES2150_E,
    PRV_CPSS_CH3_POLICER_RES2151_E,
    PRV_CPSS_CH3_POLICER_RES2152_E,
    PRV_CPSS_CH3_POLICER_RES2153_E,
    PRV_CPSS_CH3_POLICER_RES2154_E,
    PRV_CPSS_CH3_POLICER_RES2155_E,
    PRV_CPSS_CH3_POLICER_RES2156_E,
    PRV_CPSS_CH3_POLICER_RES2157_E,
    PRV_CPSS_CH3_POLICER_RES2158_E,
    PRV_CPSS_CH3_POLICER_RES2159_E,
    PRV_CPSS_CH3_POLICER_RES2160_E,
    PRV_CPSS_CH3_POLICER_RES2161_E,
    PRV_CPSS_CH3_POLICER_RES2162_E,
    PRV_CPSS_CH3_POLICER_RES2163_E,
    PRV_CPSS_CH3_POLICER_RES2164_E,
    PRV_CPSS_CH3_POLICER_RES2165_E,
    PRV_CPSS_CH3_POLICER_RES2166_E,
    PRV_CPSS_CH3_POLICER_RES2167_E,
    PRV_CPSS_CH3_POLICER_RES2168_E,
    PRV_CPSS_CH3_POLICER_RES2169_E,
    PRV_CPSS_CH3_POLICER_RES2170_E,
    PRV_CPSS_CH3_POLICER_RES2171_E,
    PRV_CPSS_CH3_POLICER_RES2172_E,
    PRV_CPSS_CH3_POLICER_RES2173_E,

    PRV_CPSS_CH3_LAST_INT_E

}PRV_CPSS_CH3_INT_CAUSE_ENT;


#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __prvCpssDrvExMxEventsCheetah3h */

